?? s2413addr.inc
字號:
;====================================================================
; File Name : 2413addr.a
; Function : S3C2413 Define Address Register (Assembly)
; Program : Shin, On Pil (SOP)
; Date : March 27, 2002
; Version : 0.0
; History
; 0.0 : Programming start (February 18,2002) -> SOP
;====================================================================
GBLL BIG_ENDIAN__
BIG_ENDIAN__ SETL {FALSE}
;=================
; Memory control
;=================
;//chapter1 EBI controller
EBIPR EQU 0x48800000 ;//Bus priority decision
BANK_CFG EQU 0x48800004 ;//Bank Configuration
;;//chapter3 MOBILE DRAM CONTROLLER
BANKCFG EQU 0x48000000 ;;//Mobile DRAM configuration
BANKCON1 EQU 0x48000004 ;;//Mobile DRAM control
BANKCON2 EQU 0x48000008 ;;//Mobile DRAM timing control
BANKCON3 EQU 0x4800000C ;;//Mobile DRAM (E)MRS
REFRESH EQU 0x48000010 ;;//Mobile DRAM refresh control
TIMEOUT EQU 0x48000014 ;;//Write Buffer Time out control
;//chapter4 SSMC
SMBIDCYR0 EQU 0x4F000000 ;//Bank0 idle cycle control
SMBIDCYR1 EQU 0x4F000020 ;//Bank1 idle cycle control
SMBIDCYR2 EQU 0x4F000040 ;//Bank2 idle cycle control
SMBIDCYR3 EQU 0x4F000060 ;//Bank3 idle cycle control
SMBIDCYR4 EQU 0x4F000080 ;//Bank0 idle cycle control
SMBIDCYR5 EQU 0x4F0000A0 ;//Bank5 idle cycle control
SMBWSTRDR0 EQU 0x4F000004 ;//Bank0 read wait state control
SMBWSTRDR1 EQU 0x4F000024 ;//Bank1 read wait state control
SMBWSTRDR2 EQU 0x4F000044 ;//Bank2 read wait state control
SMBWSTRDR3 EQU 0x4F000064 ;//Bank3 read wait state control
SMBWSTRDR4 EQU 0x4F000084 ;//Bank4 read wait state control
SMBWSTRDR5 EQU 0x4F0000A4 ;//Bank5 read wait state control
SMBWSTWRR0 EQU 0x4F000008 ;//Bank0 write wait state control
SMBWSTWRR1 EQU 0x4F000028 ;//Bank1 write wait state control
SMBWSTWRR2 EQU 0x4F000048 ;//Bank2 write wait state control
SMBWSTWRR3 EQU 0x4F000068 ;//Bank3 write wait state control
SMBWSTWRR4 EQU 0x4F000088 ;//Bank4 write wait state control
SMBWSTWRR5 EQU 0x4F0000A8 ;//Bank5 write wait state control
SMBWSTOENR0 EQU 0x4F00000C ;//Bank0 output enable assertion delay control
SMBWSTOENR1 EQU 0x4F00002C ;//Bank1 output enable assertion delay control
SMBWSTOENR2 EQU 0x4F00004C ;//Bank2 output enable assertion delay control
SMBWSTOENR3 EQU 0x4F00006C ;//Bank3 output enable assertion delay control
SMBWSTOENR4 EQU 0x4F00008C ;//Bank4 output enable assertion delay control
SMBWSTOENR5 EQU 0x4F0000AC ;//Bank5 output enable assertion delay control
SMBWSTWENR0 EQU 0x4F000010 ;//Bank0 write enable assertion delay control
SMBWSTWENR1 EQU 0x4F000030 ;//Bank1 write enable assertion delay control
SMBWSTWENR2 EQU 0x4F000050 ;//Bank2 write enable assertion delay control
SMBWSTWENR3 EQU 0x4F000070 ;//Bank3 write enable assertion delay control
SMBWSTWENR4 EQU 0x4F000090 ;//Bank4 write enable assertion delay control
SMBWSTWENR5 EQU 0x4F0000B0 ;//Bank5 write enable assertion delay control
SMBCR0 EQU 0x4F000014 ;//Bank0 control
SMBCR1 EQU 0x4F000034 ;//Bank1 control
SMBCR2 EQU 0x4F000054 ;//Bank2 control
SMBCR3 EQU 0x4F000074 ;//Bank3 control
SMBCR4 EQU 0x4F000094 ;//Bank4 control
SMBCR5 EQU 0x4F0000B4 ;//Bank5 control
SMBSR0 EQU 0x4F000018 ;//Bank0 status
SMBSR1 EQU 0x4F000038 ;//Bank1 status
SMBSR2 EQU 0x4F000058 ;//Bank2 status
SMBSR3 EQU 0x4F000078 ;//Bank3 status
SMBSR4 EQU 0x4F000098 ;//Bank4 status
SMBSR5 EQU 0x4F0000B8 ;//Bank5 status
SMBWSTBRDR0 EQU 0x4F00001C ;//Bank0 burst read wait delay control
SMBWSTBRDR1 EQU 0x4F00003C ;//Bank1 burst read wait delay control
SMBWSTBRDR2 EQU 0x4F00005C ;//Bank2 burst read wait delay control
SMBWSTBRDR3 EQU 0x4F00007C ;//Bank3 burst read wait delay control
SMBWSTBRDR4 EQU 0x4F00009C ;//Bank4 burst read wait delay control
SMBWSTBRDR5 EQU 0x4F0000BC ;//Bank5 burst read wait delay control
SSMCSR EQU 0x4F000200 ;//SROMC status
SSMCCR EQU 0x4F000204 ;//SROMC control
;=================
; USB Host
;=================
;=================
; INTERRUPT
;=================
SRCPND EQU 0x4a000000 ;//Interrupt request status
INTMOD EQU 0x4a000004 ;//Interrupt mode control
INTMSK EQU 0x4a000008 ;//Interrupt mask control
PRIORITY EQU 0x4a00000c ;//IRQ priority control
INTPND EQU 0x4a000010 ;//Interrupt request status
INTOFFSET EQU 0x4a000014 ;//Interrupt request source offset
SUBSRCPND EQU 0x4a000018 ;//Interrupt request status
INTSUBMSK EQU 0x4a00001c ;//Interrupt source mask
;=================
; DMA
;=================
DISRC0 EQU 0x4b000000 ;DMA 0 Initial source
DISRCC0 EQU 0x4b000004 ;DMA 0 Initial source control
DIDST0 EQU 0x4b000008 ;DMA 0 Initial Destination
DIDSTC0 EQU 0x4b00000c ;DMA 0 Initial Destination control
DCON0 EQU 0x4b000010 ;DMA 0 Control
DSTAT0 EQU 0x4b000014 ;DMA 0 Status
DCSRC0 EQU 0x4b000018 ;DMA 0 Current source
DCDST0 EQU 0x4b00001c ;DMA 0 Current destination
DMASKTRIG0 EQU 0x4b000020 ;DMA 0 Mask trigger
DMAREQSEL0 EQU 0x4b000024 ;DMA 0 Request Selection register
DISRC1 EQU 0x4b000040 ;DMA 1 Initial source
DISRCC1 EQU 0x4b000044 ;DMA 1 Initial source control
DIDST1 EQU 0x4b000048 ;DMA 1 Initial Destination
DIDSTC1 EQU 0x4b00004c ;DMA 1 Initial Destination control
DCON1 EQU 0x4b000050 ;DMA 1 Control
DSTAT1 EQU 0x4b000054 ;DMA 1 Status
DCSRC1 EQU 0x4b000058 ;DMA 1 Current source
DCDST1 EQU 0x4b00005c ;DMA 1 Current destination
DMASKTRIG1 EQU 0x4b000060 ;DMA 1 Mask trigger
DMAREQSEL1 EQU 0x4b000064 ;DMA 0 Request Selection register
DISRC2 EQU 0x4b000080 ;DMA 2 Initial source
DISRCC2 EQU 0x4b000084 ;DMA 2 Initial source control
DIDST2 EQU 0x4b000088 ;DMA 2 Initial Destination
DIDSTC2 EQU 0x4b00008c ;DMA 2 Initial Destination control
DCON2 EQU 0x4b000090 ;DMA 2 Control
DSTAT2 EQU 0x4b000094 ;DMA 2 Status
DCSRC2 EQU 0x4b000098 ;DMA 2 Current source
DCDST2 EQU 0x4b00009c ;DMA 2 Current destination
DMASKTRIG2 EQU 0x4b0000a0 ;DMA 2 Mask trigger
DMAREQSEL2 EQU 0x4b0000a4 ;DMA 0 Request Selection register
DISRC3 EQU 0x4b0000c0 ;DMA 3 Initial source
DISRCC3 EQU 0x4b0000c4 ;DMA 3 Initial source control
DIDST3 EQU 0x4b0000c8 ;DMA 3 Initial Destination
DIDSTC3 EQU 0x4b0000cc ;DMA 3 Initial Destination control
DCON3 EQU 0x4b0000d0 ;DMA 3 Control
DSTAT3 EQU 0x4b0000d4 ;DMA 3 Status
DCSRC3 EQU 0x4b0000d8 ;DMA 3 Current source
DCDST3 EQU 0x4b0000dc ;DMA 3 Current destination
DMASKTRIG3 EQU 0x4b0000e0 ;DMA 3 Mask trigger
DMAREQSEL3 EQU 0x4b0000e4 ;DMA 0 Request Selection register
;==========================
; CLOCK & POWER MANAGEMENT
;==========================
LOCKTIME EQU 0x4C000000 ;//MPLL/UPLL lock time conuter
MPLLCON EQU 0x4C000004 ;//MPLL configuration
UPLLCON EQU 0x4C000008 ;//UPLL configuration
CLKCON EQU 0x4C00000C ;//Clock generator control
CLKDIVN EQU 0x4C000014 ;//Clock divider control
OSCSET EQU 0x4C000018 ;//Oscillator stabilization time counter
CLKSRC EQU 0x4C00001C ;//Clock source control
PWRMODECON EQU 0x4C000020 ;//Power management mode setting
PWRCFG EQU 0x4C000024 ;//Power management configuration
WKUPSTAT EQU 0x4C000028 ;//Wakup status
ENDIAN EQU 0x4C00002C ;//System endian control
SWRSTCON EQU 0x4C000030 ;//S/W reset control
RSTCON EQU 0x4C000034 ;//Reset control
RSTSTAT EQU 0x4C000038 ;//Reset status
INFORM0 EQU 0x4C000070 ;//User defined informtion
INFORM1 EQU 0x4C000074 ;//User defined informtion
INFORM2 EQU 0x4C000078 ;//User defined informtion
INFORM3 EQU 0x4C00007C ;//User defined informtion
;=================
; LCD CONTROLLER
;=================
LCDCON1 EQU (0x4d000000) ;//LCD control 1
LCDCON2 EQU (0x4d000004) ;//LCD control 2
LCDCON3 EQU (0x4d000008) ;//LCD control 3
LCDCON4 EQU (0x4d00000c) ;//LCD control 4
LCDCON5 EQU (0x4d000010) ;//LCD control 5
LCDCON6 EQU (0x4d000034) ;//LCD control 6
LCDCON7 EQU (0x4d000038) ;//LCD control 7
LCDCON8 EQU (0x4d00003C) ;//LCD control 8
LCDCON9 EQU (0x4d000040) ;//LCD control 9
LCDSADDR1 EQU (0x4d000014) ;//STN/TFT Frame buffer start address 1
LCDSADDR2 EQU (0x4d000018) ;//STN/TFT Frame buffer start address 2
LCDSADDR3 EQU (0x4d00001c) ;//STN/TFT Virtual screen address set
TPAL EQU (0x4d000020) ;//TFT Temporary plette
;//GREENLUT EQU (0x4d000024) ;//STN Green lookup table
;//BLUELUT EQU (0x4d000028) ;//STN Blue lookup table
;//DITHMODE EQU (0x4d00004c) ;//STN Dithering mode
;//TPAL EQU (0x4d000050) ;//TFT Temporary palette
LCDINTPND EQU (0x4d000024) ;//LCD Interrupt pending
LCDSRCPND EQU (0x4d000028) ;//LCD Interrupt source
LCDINTMSK EQU (0x4d00002c) ;//LCD Interrupt mask
TCONSEL EQU (0x4d000030) ;//LPC3600 Control --- edited by junon
REDLUT0 EQU (0x4d000044) ;//Red Lookup table[31:0]
REDLUT1 EQU (0x4d000048) ;//Red Lookup table[63:32]
REDLUT2 EQU (0x4d00004C) ;//Red Lookup table[95:64]
REDLUT3 EQU (0x4d000050) ;//Red Lookup table[127:96]
REDLUT4 EQU (0x4d000054) ;//Red Lookup table[159:128]
REDLUT5 EQU (0x4d000058) ;//Red Lookup table[191:160]
REDLUT6 EQU (0x4d00005C) ;//Red Lookup table[223:192]
GREENLUT0 EQU (0x4d000060) ;//GREEN Lookup table[31:0]
GREENLUT1 EQU (0x4d000064) ;//GREEN Lookup table[63:32]
GREENLUT2 EQU (0x4d000068) ;//GREEN Lookup table[95:64]
GREENLUT3 EQU (0x4d00006C) ;//GREEN Lookup table[127:96]
GREENLUT4 EQU (0x4d000070) ;//GREEN Lookup table[159:128]
GREENLUT5 EQU (0x4d000074) ;//GREEN Lookup table[191:160]
GREENLUT6 EQU (0x4d000078) ;//GREEN Lookup table[223:192]
GREENLUT7 EQU (0x4d00007C) ;//GREEN Lookup table[255:224]
GREENLUT8 EQU (0x4d000080) ;//GREEN Lookup table[287:256]
GREENLUT9 EQU (0x4d000084) ;//GREEN Lookup table[319:288]
GREENLUT10 EQU (0x4d000088) ;//GREEN Lookup table[351:320]
GREENLUT11 EQU (0x4d00008C) ;//GREEN Lookup table[383:352]
GREENLUT12 EQU (0x4d000090) ;//GREEN Lookup table[415:384]
GREENLUT13 EQU (0x4d000094) ;//GREEN Lookup table[447:416]
BLUELUT0 EQU (0x4d000098) ;//BLUE Lookup table[31:0]
BLUELUT1 EQU (0x4d00009C) ;//BLUE Lookup table[63:32]
BLUELUT2 EQU (0x4d0000A0) ;//BLUE Lookup table[95:64]
BLUELUT3 EQU (0x4d0000A4) ;//BLUE Lookup table[127:96]
BLUELUT4 EQU (0x4d0000A8) ;//BLUE Lookup table[159:128]
BLUELUT5 EQU (0x4d0000AC) ;//BLUE Lookup table[191:160]
BLUELUT6 EQU (0x4d0000B0) ;//BLUE Lookup table[223:192]
FRCPAT0 EQU (0x4d0000B4) ;//FRC Pattern
FRCPAT1 EQU (0x4d0000B8) ;//FRC Pattern
FRCPAT2 EQU (0x4d0000BC) ;//FRC Pattern
FRCPAT3 EQU (0x4d0000C0) ;//FRC Pattern
FRCPAT4 EQU (0x4d0000C4) ;//FRC Pattern
FRCPAT5 EQU (0x4d0000C8) ;//FRC Pattern
FRCPAT6 EQU (0x4d0000CC) ;//FRC Pattern
FRCPAT7 EQU (0x4d0000D0) ;//FRC Pattern
FRCPAT8 EQU (0x4d0000D4) ;//FRC Pattern
FRCPAT9 EQU (0x4d0000D8) ;//FRC Pattern
FRCPAT10 EQU (0x4d0000DC) ;//FRC Pattern
FRCPAT11 EQU (0x4d0000E0) ;//FRC Pattern
FRCPAT12 EQU (0x4d0000E4) ;//FRC Pattern
FRCPAT13 EQU (0x4d0000E8) ;//FRC Pattern
FRCPAT14 EQU (0x4d0000EC) ;//FRC Pattern
FRCPAT15 EQU (0x4d0000F0) ;//FRC Pattern
FRCPAT16 EQU (0x4d0000F4) ;//FRC Pattern
FRCPAT17 EQU (0x4d0000F8) ;//FRC Pattern
FRCPAT18 EQU (0x4d0000FC) ;//FRC Pattern
FRCPAT19 EQU (0x4d000100) ;//FRC Pattern
FRCPAT20 EQU (0x4d000104) ;//FRC Pattern
FRCPAT21 EQU (0x4d000108) ;//FRC Pattern
FRCPAT22 EQU (0x4d00010C) ;//FRC Pattern
FRCPAT23 EQU (0x4d000110) ;//FRC Pattern
FRCPAT24 EQU (0x4d000114) ;//FRC Pattern
FRCPAT25 EQU (0x4d000118) ;//FRC Pattern
FRCPAT26 EQU (0x4d00011C) ;//FRC Pattern
FRCPAT27 EQU (0x4d000120) ;//FRC Pattern
FRCPAT28 EQU (0x4d000124) ;//FRC Pattern
FRCPAT29 EQU (0x4d000128) ;//FRC Pattern
FRCPAT30 EQU (0x4d00012C) ;//FRC Pattern
FRCPAT31 EQU (0x4d000130) ;//FRC Pattern
FRCPAT32 EQU (0x4d000134) ;//FRC Pattern
FRCPAT33 EQU (0x4d000138) ;//FRC Pattern
FRCPAT34 EQU (0x4d00013C) ;//FRC Pattern
FRCPAT35 EQU (0x4d000140) ;//FRC Pattern
FRCPAT36 EQU (0x4d000144) ;//FRC Pattern
FRCPAT37 EQU (0x4d000148) ;//FRC Pattern
FRCPAT38 EQU (0x4d00014C) ;//FRC Pattern
FRCPAT39 EQU (0x4d000150) ;//FRC Pattern
FRCPAT40 EQU (0x4d000154) ;//FRC Pattern
FRCPAT41 EQU (0x4d000158) ;//FRC Pattern
FRCPAT42 EQU (0x4d00015C) ;//FRC Pattern
FRCPAT43 EQU (0x4d000160) ;//FRC Pattern
FRCPAT44 EQU (0x4d000164) ;//FRC Pattern
FRCPAT45 EQU (0x4d000168) ;//FRC Pattern
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