Release 9.1i - xst J.30Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.00 / 2.62 s | Elapsed : 0.00 / 2.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 2.64 s | Elapsed : 0.00 / 2.00 s --> Reading design: CANtoFDDI.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) Design Hierarchy Analysis  4) HDL Analysis  5) HDL Synthesis     5.1) HDL Synthesis Report  6) Advanced HDL Synthesis     6.1) Advanced HDL Synthesis Report  7) Low Level Synthesis  8) Partition Report  9) Final Report=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "CANtoFDDI.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "CANtoFDDI"Output Format                      : NGCTarget Device                      : XC9500 CPLDs---- Source OptionsTop Module Name                    : CANtoFDDIAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoSafe Implementation                : NoMux Extraction                     : YESResource Sharing                   : YES---- Target OptionsAdd IO Buffers                     : YESMACRO Preserve                     : YESXOR Preserve                       : YESEquivalent register Removal        : YES---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Library Search Order               : CANtoFDDI.lsoKeep Hierarchy                     : YESRTL Output                         : YesHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainVerilog 2001                       : YES---- Other Optionswysiwyg                            : NO==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "232-fddi.v" in library workModule <CANtoFDDI> compiledNo errors in compilationAnalysis of file <"CANtoFDDI.prj"> succeeded. =========================================================================*                     Design Hierarchy Analysis                         *=========================================================================Analyzing hierarchy for module <CANtoFDDI> in library <work>.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <CANtoFDDI>.Module <CANtoFDDI> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Performing bidirectional port resolution...Synthesizing Unit <CANtoFDDI>.    Related source file is "232-fddi.v".WARNING:Xst:1780 - Signal <cTX_Start> is never used or assigned.WARNING:Xst - Property "use_dsp48" is not applicable for this technology.WARNING:Xst - Property "use_dsp48" is not applicable for this technology.    Found 4-bit register for signal <cTX_Data>.    Found 3-bit comparator greatequal for signal <cTX_Data_0$cmp_ge0000> created at line 130.    Found 3-bit comparator greater for signal <cTX_Data_0$cmp_gt0000> created at line 141.    Found 4-bit comparator lessequal for signal <cTX_Data_0$cmp_le0000> created at line 128.    Found 3-bit up counter for signal <cTX_DataN>.    Found 3-bit comparator greater for signal <cTX_DataN$cmp_gt0000> created at line 141.    Found 1-bit register for signal <cTX_Tem>.    Found 3-bit comparator lessequal for signal <cTX_Tem$cmp_le0000> created at line 141.    Found 4-bit up counter for signal <fBit_Bit>.    Found 4-bit comparator greater for signal <fBit_Bit$cmp_gt0000> created at line 128.    Found 1-bit xor2 for signal <fBit_Bit$xor0000> created at line 117.    Found 1-bit register for signal <fBit_Value>.    Found 4-bit up counter for signal <fTX_CLK>.    Found 4-bit comparator less for signal <fTX_CLK$cmp_lt0000> created at line 181.    Found 1-bit register for signal <fTX_N>.    Found 1-bit register for signal <fTX_Over>.    Found 1-bit register for signal <fTX_Start>.    Found 1-bit register for signal <fTX_T>.    Found 1-bit register for signal <fTX_Tem>.    Found 1-bit register for signal <LED_RXTem>.    Found 1-bit register for signal <LED_TXTem>.    Found 3-bit adder for signal <old_cTX_DataN_2$add0000> created at line 140.    Found 4-bit adder for signal <old_fBit_Bit_1$add0000> created at line 127.    Summary:	inferred   3 Counter(s).	inferred  11 D-type flip-flop(s).	inferred   2 Adder/Subtractor(s).	inferred   7 Comparator(s).	inferred   1 Xor(s).Unit <CANtoFDDI> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors                                   : 2 3-bit adder                                           : 1 4-bit adder                                           : 1# Counters                                             : 3 3-bit up counter                                      : 1 4-bit up counter                                      : 2# Registers                                            : 13 1-bit register                                        : 13# Comparators                                          : 7 3-bit comparator greatequal                           : 1 3-bit comparator greater                              : 2 3-bit comparator lessequal                            : 1 4-bit comparator greater                              : 1 4-bit comparator less                                 : 1 4-bit comparator lessequal                            : 1# Xors                                                 : 1 1-bit xor2                                            : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================Advanced HDL Synthesis ReportMacro Statistics# Adders/Subtractors                                   : 2 3-bit adder                                           : 1 4-bit adder                                           : 1# Counters                                             : 3 3-bit up counter                                      : 1 4-bit up counter                                      : 2# Registers                                            : 13 Flip-Flops                                            : 13==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <CANtoFDDI> ...  implementation constraint: INIT=r	 : fBit_Bit_1  implementation constraint: INIT=r	 : fTX_Tem  implementation constraint: INIT=r	 : LED_TXTem  implementation constraint: INIT=r	 : LED_RXTem  implementation constraint: INIT=r	 : cTX_Data_0  implementation constraint: INIT=s	 : fTX_Start  implementation constraint: INIT=r	 : cTX_Data_1  implementation constraint: INIT=r	 : cTX_Data_2  implementation constraint: INIT=r	 : cTX_Data_3  implementation constraint: INIT=r	 : fTX_N  implementation constraint: INIT=r	 : fBit_Bit_3  implementation constraint: INIT=r	 : fTX_Over  implementation constraint: INIT=r	 : fTX_CLK_0  implementation constraint: INIT=r	 : fTX_CLK_1  implementation constraint: INIT=r	 : fTX_CLK_2  implementation constraint: INIT=r	 : fTX_CLK_3  implementation constraint: INIT=r	 : fBit_Bit_2  implementation constraint: INIT=r	 : cTX_DataN_2  implementation constraint: INIT=r	 : cTX_DataN_1  implementation constraint: INIT=r	 : cTX_DataN_0  implementation constraint: INIT=r	 : fBit_Bit_0WARNING:Xst:1293 - FF/Latch  <cTX_DataN_2> has a constant value of 0 in block <CANtoFDDI>.WARNING:Xst:1293 - FF/Latch  <fBit_Bit_3> has a constant value of 0 in block <CANtoFDDI>.WARNING:Xst:1293 - FF/Latch  <fBit_Bit_2> has a constant value of 0 in block <CANtoFDDI>.=========================================================================*                          Partition Report                             *=========================================================================Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : CANtoFDDI.ngrTop Level Output File Name         : CANtoFDDIOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : YESTarget Technology                  : XC9500 CPLDsMacro Preserve                     : YESXOR Preserve                       : YESwysiwyg                            : NODesign Statistics# IOs                              : 8Cell Usage :# BELS                             : 198#      AND2                        : 71#      AND3                        : 4#      AND4                        : 2#      INV                         : 72#      OR2                         : 38#      OR3                         : 2#      XOR2                        : 9# FlipFlops/Latches                : 21#      FD                          : 21# IO Buffers                       : 8#      IBUF                        : 4#      OBUF                        : 4=========================================================================CPU : 5.66 / 8.34 s | Elapsed : 5.00 / 8.00 s --> Total memory usage is 134732 kilobytesNumber of errors   :    0 (   0 filtered)Number of warnings :    6 (   0 filtered)Number of infos    :    0 (   0 filtered)