+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+
; cpu.vhd                          ; yes             ; Other     ; C:/altera/VHDL/chap4/cpu.vhd ;
+----------------------------------+-----------------+-----------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 667   ;
;     -- Combinational with no register       ; 575   ;
;     -- Register only                        ; 24    ;
;     -- Combinational with a register        ; 68    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 400   ;
;     -- 3 input functions                    ; 159   ;
;     -- 2 input functions                    ; 83    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 592   ;
;     -- arithmetic mode                      ; 75    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 48    ;
;     -- asynchronous clear/load mode         ; 91    ;
;                                             ;       ;
; Total registers                             ; 92    ;
; Total logic cells in carry chains           ; 84    ;
; I/O pins                                    ; 32    ;
; Maximum fan-out node                        ; reset ;
; Maximum fan-out                             ; 93    ;
; Total fan-out                               ; 2640  ;
; Average fan-out                             ; 3.78  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |cpu                       ; 667 (667)   ; 92           ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 32   ; 0            ; 575 (575)    ; 24 (24)           ; 68 (68)          ; 84 (84)         ; 0 (0)      ; |cpu                ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 92    ;
; Number of registers using Synchronous Clear  ; 6     ;
; Number of registers using Synchronous Load   ; 42    ;
; Number of registers using Asynchronous Clear ; 91    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 89    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 7:1                ; 8 bits    ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |cpu|IR[12]                ;
; 8:1                ; 8 bits    ; 40 LEs        ; 0 LEs                ; 40 LEs                 ; Yes        ; |cpu|MDR[0]                ;
; 22:1               ; 8 bits    ; 112 LEs       ; 0 LEs                ; 112 LEs                ; Yes        ; |cpu|\seq:A[5]             ;
; 12:1               ; 8 bits    ; 64 LEs        ; 8 LEs                ; 56 LEs                 ; Yes        ; |cpu|IR[6]                 ;
; 14:1               ; 12 bits   ; 108 LEs       ; 24 LEs               ; 84 LEs                 ; Yes        ; |cpu|MAR[2]                ;
; 15:1               ; 12 bits   ; 120 LEs       ; 24 LEs               ; 96 LEs                 ; Yes        ; |cpu|\seq:PC[7]            ;
; 42:1               ; 6 bits    ; 168 LEs       ; 48 LEs               ; 120 LEs                ; Yes        ; |cpu|\seq:R1[6]            ;
; 42:1               ; 6 bits    ; 168 LEs       ; 48 LEs               ; 120 LEs                ; Yes        ; |cpu|\seq:R2[1]            ;
; 42:1               ; 6 bits    ; 168 LEs       ; 48 LEs               ; 120 LEs                ; Yes        ; |cpu|\seq:R3[5]            ;
; 44:1               ; 3 bits    ; 87 LEs        ; 27 LEs               ; 60 LEs                 ; Yes        ; |cpu|\seq:R0[4]            ;
; 46:1               ; 3 bits    ; 90 LEs        ; 27 LEs               ; 63 LEs                 ; Yes        ; |cpu|\seq:R0[3]            ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |cpu|Mux8                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-----------------------------------------------+
; Source assignments for Top-level Entity: |cpu ;
+----------------+-------+------+---------------+
; Assignment     ; Value ; From ; To            ;
+----------------+-------+------+---------------+
; POWER_UP_LEVEL ; Low   ; -    ; status[0]     ;
; POWER_UP_LEVEL ; Low   ; -    ; status[1]     ;
; POWER_UP_LEVEL ; Low   ; -    ; status[2]     ;
+----------------+-------+------+---------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Wed Nov 21 20:04:08 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu -c cpu
Warning: Using design file cpu.vhd, which is not specified as a design file for the current project, but contains definitions for 3 design units and 1 entities in project
    Info: Found design unit 1: namespack
    Info: Found design unit 2: cpu-RTL
    Info: Found entity 1: cpu
Info: Elaborating entity "cpu" for the top level hierarchy
Info: Implemented 699 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 22 output pins
    Info: Implemented 667 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Nov 21 20:04:43 2007
    Info: Elapsed time: 00:00:35