.text	.align 4 	.global begin	.type begin,functionbegin:	@set the IRQ stack	mov 	r0, #0xd2          @IRQMode	msr	cpsr_c,r0 	   @IRQMode	ldr	sp,=IRQstack_beg	        mov	r0, #211   					@ make sure svc mode	msr	CPSR_c, r0					@ and all irqs disabled        adr	r5, startup_data			        ldmia	r5, {r5, r8, sp}			@ Setup bss and stack , r5 is length        /*  Copy data sections to their new home.  */        /* r8 is bss addr */        /*  Clear BSS */	1:      mov	r4, #0        str	r4, [r8],#4	sub     r5, r5, #1		cmp 	r5, #0        bgt	1b		/*set the irq vector in 0x18*//*	mov	r4, #0	adr	r5, except_vector12:	ldr	r2, [r5,r4]	str	r2, [r4]	add	r4,r4,#4	cmp	r4, #32	ble	2b*/			        /*  Pretend we know what our processor code is (for arm_id)   */@@@	ldr     r2, =0x41000000@@@	orr	r2, r2, #0x7000		@ FIXME --> 0x41007000	ldr	r2, L_AT91_SF_CIDR	ldr	r2, [r2]		@ read processor id	str     r2, pid_adr	/* MACH_TYPE_ATMEL is 89 0x59 */	mov     r2, #89	str     r2, mid_adr		/* at91_init*/	mov fp, #0	bl	init_kernel	        mov fp, #0        b	start_kernel	__error:1:	mov	r0, r0	b	1b/*---------------------------------except_vector1:__error1:	b	__error1__error2:	b	__error2__error3:	b	__error3__error4:	b	__error4__error5:	b	__error5__error6:	b	__error6__error7:  	b	__error7__error8:	b	__error8__stubs_start:vector_reset:		b vector_resetvector_undefinstr:		b vector_undefinstrvector_swi:			b vector_swivector_prefetch:		b vector_prefetchvector_data:		b vector_datavector_addrexcptn:		b vector_addrexcptn------------------------------------*//* * Interrupt dispatcher * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC *//*-------------------------------------------------------vector_IRQ:	@		@ save mode specific registers		@		ldr	r13, .LCsirq		sub	lr, lr, #4		str	lr, [r13]			@ save lr_IRQ		mrs	lr, spsr		str	lr, [r13, #4]			@ save spsr_IRQ		@		@ now branch to the relevent MODE handling routine		@		mrs	r13, spsr			@ switch to SVC_32 mode		bic	r13, r13, #MODE_MASK		@ preserve F and T bits		orr	r13, r13, #MODE_SVC|I_BIT		msr	spsr_c, r13			@ switch to SVC_32 mode		and	lr, lr, #15		ldr	lr, [pc, lr, lsl #2]		movs	pc, lr				@ Changes mode and branches.LCtab_irq:	.word	__irq_usr			@  0  (USR_26 / USR_32)		.word	__irq_invalid			@  1  (FIQ_26 / FIQ_32)		.word	__irq_invalid			@  2  (IRQ_26 / IRQ_32)		.word	__irq_svc			@  3  (SVC_26 / SVC_32)		.word	__irq_invalid			@  4		.word	__irq_invalid			@  5		.word	__irq_invalid			@  6		.word	__irq_invalid			@  7		.word	__irq_invalid			@  8		.word	__irq_invalid			@  9		.word	__irq_invalid			@  a		.word	__irq_invalid			@  b		.word	__irq_invalid			@  c		.word	__irq_invalid			@  d		.word	__irq_invalid			@  e		.word	__irq_invalid			@  f------------------------------------------------*//*---------------------------------------------__stubs_end:		.equ	__real_stubs_start, .LCvectors + 0x200.LCvectors:	b	__real_stubs_start + (vector_reset - __stubs_start)		b	__real_stubs_start + (vector_undefinstr - __stubs_start)		b	__real_stubs_start + (vector_swi - __stubs_start)		b	__real_stubs_start + (vector_prefetch - __stubs_start)		b	__real_stubs_start + (vector_data - __stubs_start)		b	__real_stubs_start + (vector_addrexcptn - __stubs_start)		b	__real_stubs_start + (vector_IRQ - __stubs_start)		b	__real_stubs_start + (vector_FIQ - __stubs_start)ENTRY(__trap_init)		stmfd	sp!, {r4 - r6, lr}		mrs	r1, cpsr		@ code from 2.0.38		bic	r1, r1, #MODE_MASK	@ clear mode bits		orr	r1, r1, #I_BIT|F_BIT|MODE_SVC	@ set SVC mode, disable IRQ,FIQ		msr	cpsr, r1		adr	r1, .LCvectors			@ set up the vectors		ldmia	r1, {r1, r2, r3, r4, r5, r6, ip, lr}		stmia	r0, {r1, r2, r3, r4, r5, r6, ip, lr}		add	r2, r0, #0x200		adr	r0, __stubs_start		@ copy stubs to 0x200		adr	r1, __stubs_end1:		ldr	r3, [r0], #4		str	r3, [r2], #4		cmp	r0, r1		blt	1b------------------------------------------*/   @----------------------------------------------------------------------      	.align  2        .global ARMDisableInt	.type    ARMDisableInt,functionARMDisableInt:         STMDB   sp!, {r0}         MRS     r0, CPSR         ORR     r0, r0, #0x80		@NoInterrupt         MSR     CPSR_c, r0         LDMIA   sp!, {r0}	 MOV     pc, lr	    @------------------------------------------------------------------------        .align  2        .global ARMEnableInt        .type    ARMEnableInt,functionARMEnableInt:        STMDB   sp!, {r0}        MRS     r0, CPSR        BIC     r0, r0, #0x80		@NoInterrupt        MSR     CPSR_c, r0        LDMIA   sp!, {r0}        MOV     pc, lr   @------------------------------------------------------------------------        .align  2        .global AT91_IRQHandler         .type    AT91_IRQHandler,functionAT91_IRQHandler:	@Interrupt Handler Prologue	SUB	lr, lr, #4	STMFD	sp!, {r0-r12, lr}		@; push registers and return address	MRS	r4, SPSR			@; get SPSR	STMFD	sp!, {r4}			@; push SPSR	@; End Interrupt Handler Prologue	@; Call main IRQ service dispatcher	BL do_IRQ		/* chy test	LDR	r12, =swap_context_flag 	LDR	r11, [r12]	TST	r11, #1	BEQ	%99	MOV r11, #0	STR	r11, [r12]	B	IRQContextSwap	*/		@; Interrupt Handler Epilogue	LDMFD	sp!, {r4}			@; pop SPSR		MSR	SPSR_c, r4			@; restore SPSR	LDMFD	sp!, {r0-r12, pc}^		@; restore registers and RFI	@; End Interrupt Handler Epilogue	@;	@; End of IRQHandler	@;/*	        .align  2	.global _gccmain	.type    main,function__gccmain:mainloop:	mov	r0, r0	b	1b*/L_AT91_SF_CIDR: .long	0xfff00000startup_data:   	       .word	  4096	       .word      stack_beg	       .word	  bss_begpid_adr:       .word 	  proc_idmid_adr:       .word	  mach_id		.data	.align 2proc_id: .word 0mach_id: .word 0	.align 2	.type stack_beg,object	.size stack_beg,4096stack_beg:	.word  0	.space 4096stak_end:	.word	0	.space 4096IRQstack_beg:	.word	0	.space	4096IRQstack_end:	.word	0	.space	4096.bss	.align 2	.type bss_beg,object	.size bss_beg,4096bss_beg:	.word 0	.space 4096