ucos.elf:     file format elf32-littlearmDisassembly of section .text:01000000 <begin>: 1000000:	e3a000d2 	mov	r0, #210	; 0xd2 1000004:	e121f000 	msr	CPSR_c, r0 1000008:	e59fd07c 	ldr	sp, [pc, #7c]	; 100008c <mid_adr+0x4> 100000c:	e3a000d3 	mov	r0, #211	; 0xd3 1000010:	e121f000 	msr	CPSR_c, r0 1000014:	e28f505c 	add	r5, pc, #92	; 0x5c 1000018:	e8952120 	ldmia	r5, {r5, r8, sp} 100001c:	e3a04000 	mov	r4, #0	; 0x0 1000020:	e4884004 	str	r4, [r8], #4 1000024:	e2455001 	sub	r5, r5, #1	; 0x1 1000028:	e3550000 	cmp	r5, #0	; 0x0 100002c:	cafffffa 	bgt	100001c <begin+0x1c> 1000030:	e59f203c 	ldr	r2, [pc, #3c]	; 1000074 <L_AT91_SF_CIDR> 1000034:	e5922000 	ldr	r2, [r2] 1000038:	e58f2044 	str	r2, [pc, #44]	; 1000084 <pid_adr> 100003c:	e3a02059 	mov	r2, #89	; 0x59 1000040:	e58f2040 	str	r2, [pc, #40]	; 1000088 <mid_adr> 1000044:	e3a0b000 	mov	r11, #0	; 0x0 1000048:	eb000091 	bl	1000294 <init_kernel> 100004c:	e3a0b000 	mov	r11, #0	; 0x0 1000050:	ea0004c3 	b	1001364 <start_kernel>01000054 <AT91_IRQHandler>: 1000054:	e24ee004 	sub	lr, lr, #4	; 0x4 1000058:	e92d5fff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} 100005c:	e14f4000 	mrs	r4, SPSR 1000060:	e92d0010 	stmdb	sp!, {r4} 1000064:	eb000085 	bl	1000280 <do_IRQ> 1000068:	e8bd0010 	ldmia	sp!, {r4} 100006c:	e161f004 	msr	SPSR_c, r4 1000070:	e8fd9fff 	ldmia	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, pc}^01000074 <L_AT91_SF_CIDR>: 1000074:	fff00000 	swinv	0x00f00000	; IMB01000078 <startup_data>: 1000078:	00001000 	andeq	r1, r0, r0 100007c:	01002008 	tsteq	r0, r8 1000080:	01006064 	tsteq	r0, r4, rrx01000084 <pid_adr>: 1000084:	01002000 	tsteq	r0, r001000088 <mid_adr>: 1000088:	01002004 	tsteq	r0, r4 100008c:	01004010 	tsteq	r0, r0, lsl r001000090 <at91_mask_irq>: 1000090:	e1a0c00d 	mov	r12, sp 1000094:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc} 1000098:	e24cb004 	sub	r11, r12, #4	; 0x4void at91_mask_irq(unsigned int irq){	unsigned long mask = 1 << (irq); 100009c:	e3a03001 	mov	r3, #1	; 0x1 10000a0:	e1a03013 	mov	r3, r3, lsl r0	__arch_putl(mask, AIC_IDCR); 10000a4:	e3e02eed 	mvn	r2, #3792	; 0xed0 10000a8:	e502300b 	str	r3, [r2, -#11]}	 10000ac:	e91ba800 	ldmdb	r11, {r11, sp, pc}010000b0 <at91_unmask_irq>: 10000b0:	e1a0c00d 	mov	r12, sp 10000b4:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc} 10000b8:	e24cb004 	sub	r11, r12, #4	; 0x4void at91_unmask_irq(unsigned int irq){	unsigned long mask = 1 << (irq);	__arch_putl(mask, AIC_IECR); 10000bc:	e3a02489 	mov	r2, #-1996488704	; 0x89000000 10000c0:	e1a029c2 	mov	r2, r2, asr #19 10000c4:	e3a03001 	mov	r3, #1	; 0x1 10000c8:	e1a03013 	mov	r3, r3, lsl r0 10000cc:	e5823000 	str	r3, [r2]} 10000d0:	e91ba800 	ldmdb	r11, {r11, sp, pc}010000d4 <at91_mask_ack_irq>: 10000d4:	e1a0c00d 	mov	r12, sp 10000d8:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc} 10000dc:	e24cb004 	sub	r11, r12, #4	; 0x4void at91_mask_ack_irq(unsigned int irq){	at91_mask_irq(irq); 10000e0:	ebffffea 	bl	1000090 <at91_mask_irq>        __arch_putl(0, AIC_EOICR);     /* value=don't care */ 10000e4:	e3e02d3b 	mvn	r2, #3776	; 0xec0 10000e8:	e3a03000 	mov	r3, #0	; 0x0 10000ec:	e502300f 	str	r3, [r2, -#15] 10000f0:	e91ba800 	ldmdb	r11, {r11, sp, pc}010000f4 <install_irqhandler>: 10000f4:	e1a0c00d 	mov	r12, sp 10000f8:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc}}#define IRQ_VEC		0x18#define IRQ_ADDR	0x38void install_irqhandler(void){  unsigned int * irqaddr = (unsigned int *) IRQ_ADDR;  unsigned int * irqvec = (unsigned int *) IRQ_VEC;  10000fc:	e3a01018 	mov	r1, #24	; 0x18  unsigned int vec, oldvec;  /*      *irqaddr = (unsigned int) AT91_IRQHandler;  */    *irqaddr = (unsigned int) OSTickISR;    vec = ((unsigned int) irqaddr  - (unsigned int)irqvec - 0x08) | 0xe59ff000; 1000100:	e38134e5 	orr	r3, r1, #-452984832	; 0xe5000000 1000104:	e383389f 	orr	r3, r3, #10420224	; 0x9f0000 1000108:	e3833a0f 	orr	r3, r3, #61440	; 0xf000    oldvec = *irqvec;  *irqvec = vec; 100010c:	e5813000 	str	r3, [r1] 1000110:	e24cb004 	sub	r11, r12, #4	; 0x4 1000114:	e59f2008 	ldr	r2, [pc, #8]	; 1000124 <install_irqhandler+0x30> 1000118:	e3a03038 	mov	r3, #56	; 0x38 100011c:	e5832000 	str	r2, [r3]			} 1000120:	e91ba800 	ldmdb	r11, {r11, sp, pc} 1000124:	0100035c 	tsteq	r0, r12, asr r301000128 <init_timer>: 1000128:	e1a0c00d 	mov	r12, sp 100012c:	e92dd810 	stmdb	sp!, {r4, r11, r12, lr, pc} 1000130:	e24cb004 	sub	r11, r12, #4	; 0x4void init_timer(void){        register volatile struct at91_timers* tt = (struct at91_timers*) (AT91_TC_BASE); 1000134:	e3a01102 	mov	r1, #-2147483648	; 0x80000000 1000138:	e1a01741 	mov	r1, r1, asr #14        register volatile struct at91_timer_channel* tc = &tt->chans[KERNEL_TIMER].ch;        unsigned long v;        /* chy 2002-12-12, init sys_timer_count */	sys_timer_count=0; 100013c:	e3a0e000 	mov	lr, #0	; 0x0	/* enable Kernel timer  defined in at91_init.h*/	/* chy 2002-12-12, seems no use??? */	HW_AT91_TIMER_INIT(KERNEL_TIMER)        /* No SYNC */        tt->bcr = 0;        /* program NO signal on XC1 */        v = tt->bmr;	v &= ~TCNXCNS(KERNEL_TIMER,3);	v |= TCNXCNS(KERNEL_TIMER,1);        tt->bmr = v;        tc->ccr = 2;  /* disable the channel */        /* select ACLK/128 as inupt frequency for TC1 and enable CPCTRG */        tc->cmr = 3 | (1 << 14); 1000140:	e3a00901 	mov	r0, #16384	; 0x4000 1000144:	e581e0c0 	str	lr, [r1, #192] 1000148:	e2800003 	add	r0, r0, #3	; 0x3 100014c:	e59f3058 	ldr	r3, [pc, #58]	; 10001ac <init_timer+0x84>	        tc->idr = ~0ul;  /* disable all interrupt */	tc->rc = ((ARM_CLK/128)/HZ - 1);   /* load the count limit into the CR register */ 1000150:	e3a0ce9f 	mov	r12, #2544	; 0x9f0 1000154:	e59120c4 	ldr	r2, [r1, #196] 1000158:	e28cc00f 	add	r12, r12, #15	; 0xf 100015c:	e583e000 	str	lr, [r3] 1000160:	e3c2200c 	bic	r2, r2, #12	; 0xc 1000164:	e3822004 	orr	r2, r2, #4	; 0x4 1000168:	e58120c4 	str	r2, [r1, #196] 100016c:	e3a03002 	mov	r3, #2	; 0x2 1000170:	e5813040 	str	r3, [r1, #64] 1000174:	e2812040 	add	r2, r1, #64	; 0x40 1000178:	e5820004 	str	r0, [r2, #4] 100017c:	e2433003 	sub	r3, r3, #3	; 0x3 1000180:	e5823028 	str	r3, [r2, #40]	tc->ier = TC_CPCS;  /* enable CPCS interrupt */	/* enable the channel */	tc->ccr = TC_SWTRG|TC_CLKEN; 1000184:	e3a04005 	mov	r4, #5	; 0x5 1000188:	e582c01c 	str	r12, [r2, #28] 100018c:	e2833011 	add	r3, r3, #17	; 0x11 1000190:	e5823024 	str	r3, [r2, #36]		/* chy 2002-12-12 no use        gettimeoffset = atmel_gettimeoffset;		timer_irq.handler = atmel_timer_interrupt;        setup_arm_irq(KERNEL_TIMER_IRQ_NUM, &timer_irq);        */	at91_mask_ack_irq(KERNEL_TIMER_IRQ_NUM); 1000194:	e1a00004 	mov	r0, r4 1000198:	e5814040 	str	r4, [r1, #64] 100019c:	ebffffcc 	bl	10000d4 <at91_mask_ack_irq>	at91_unmask_irq(KERNEL_TIMER_IRQ_NUM); 10001a0:	e1a00004 	mov	r0, r4 10001a4:	ebffffc1 	bl	10000b0 <at91_unmask_irq>} 10001a8:	e91ba810 	ldmdb	r11, {r4, r11, sp, pc} 10001ac:	01007068 	tsteq	r0, r8, rrx010001b0 <atmel_timer_interrupt>: 10001b0:	e1a0c00d 	mov	r12, sp 10001b4:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc}void atmel_timer_interrupt(void){	/*	struct at91_timers* tt = (struct at91_timers*) (AT91_TC_BASE);	volatile struct  at91_timer_channel* tc = &tt->chans[KERNEL_TIMER].ch;	int tmp;	unsigned long v = tc->sr; 	*/        sys_timer_count++; 10001b8:	e59f2024 	ldr	r2, [pc, #24]	; 10001e4 <atmel_timer_interrupt+0x34> 10001bc:	e24cb004 	sub	r11, r12, #4	; 0x4 10001c0:	e5923000 	ldr	r3, [r2]	        /* end of timer interrupts */	at91_unmask_irq(KERNEL_TIMER_IRQ_NUM); 10001c4:	e3a00005 	mov	r0, #5	; 0x5 10001c8:	e2833001 	add	r3, r3, #1	; 0x1 10001cc:	e5823000 	str	r3, [r2] 10001d0:	ebffffb6 	bl	10000b0 <at91_unmask_irq>	__arch_putl(KERNEL_TIMER_IRQ_NUM,AIC_EOICR); 10001d4:	e3e02d3b 	mvn	r2, #3776	; 0xec0 10001d8:	e3a03005 	mov	r3, #5	; 0x5 10001dc:	e502300f 	str	r3, [r2, -#15] 10001e0:	e91ba800 	ldmdb	r11, {r11, sp, pc} 10001e4:	01007068 	tsteq	r0, r8, rrx010001e8 <at91_init_aic>: 10001e8:	e1a0c00d 	mov	r12, sp 10001ec:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc} 10001f0:	e24cb004 	sub	r11, r12, #4	; 0x4}void at91_init_aic(){        int irqno;	/* Disable all interrupts */	__arch_putl(0xFFFFFFFF, AIC_IDCR);        /* Clear all interrupts	*/        __arch_putl(0xFFFFFFFF, AIC_ICCR);        	for ( irqno = 0 ; irqno < 32 ; irqno++ ) 10001f4:	e3a01000 	mov	r1, #0	; 0x0 10001f8:	e3e02eed 	mvn	r2, #3792	; 0xed0 10001fc:	e3e03000 	mvn	r3, #0	; 0x0 1000200:	e502300b 	str	r3, [r2, -#11] 1000204:	e3e00d3b 	mvn	r0, #3776	; 0xec0 1000208:	e5023007 	str	r3, [r2, -#7]	{	       __arch_putl(irqno, AIC_EOICR); 100020c:	e500100f 	str	r1, [r0, -#15] 1000210:	e2811001 	add	r1, r1, #1	; 0x1 1000214:	e351001f 	cmp	r1, #31	; 0x1f 1000218:	dafffffb 	ble	100020c <at91_init_aic+0x24>	}        for ( irqno = 0 ; irqno < 32 ; irqno++ ) 100021c:	e3a01000 	mov	r1, #0	; 0x0 1000220:	e3a00102 	mov	r0, #-2147483648	; 0x80000000 1000224:	e59fe024 	ldr	lr, [pc, #24]	; 1000250 <at91_init_aic+0x68> 1000228:	e1a009c0 	mov	r0, r0, asr #19 100022c:	e59fc020 	ldr	r12, [pc, #20]	; 1000254 <at91_init_aic+0x6c>        {               __arch_putl((eb01_irq_prtable[irqno] >> 5) | eb01_irq_type[irqno],AIC_SMR(irqno)); 1000230:	e7de2001 	ldrb	r2, [lr, r1] 1000234:	e7dc3001 	ldrb	r3, [r12, r1] 1000238:	e18332a2 	orr	r3, r3, r2, lsr #5 100023c:	e7803101 	str	r3, [r0, r1, lsl #2] 1000240:	e2811001 	add	r1, r1, #1	; 0x1 1000244:	e351001f 	cmp	r1, #31	; 0x1f 1000248:	dafffff8 	ble	1000230 <at91_init_aic+0x48>														}} 100024c:	e91ba800 	ldmdb	r11, {r11, sp, pc} 1000250:	01006018 	tsteq	r0, r8, lsl r0 1000254:	01006038 	tsteq	r0, r8, lsr r001000258 <init_IRQ>: 1000258:	e1a0c00d 	mov	r12, sp 100025c:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc} 1000260:	e24cb004 	sub	r11, r12, #4	; 0x4														 void init_IRQ(void){  at91_init_aic(); 1000264:	ebffffdf 	bl	10001e8 <at91_init_aic>  install_irqhandler(); 1000268:	ebffffa1 	bl	10000f4 <install_irqhandler>