;/*****************************************************************************/
;/* LPC28xx.S: Startup file for Philips LPC28xx device series                 */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>>                          */ 
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools.                   */
;/* Copyright (c) 2005-2007 Keil Software. All rights reserved.               */
;/* This software may only be used under the terms of a valid, current,       */
;/* end user licence from KEIL for a compatible version of KEIL software      */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/


; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F

I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled


;----------------------- Memory Definitions ------------------------------------

; Internal Memory Base Addresses
IRAM_BASE       EQU     0x00400000
IROM_BASE       EQU     0x00200000
IFLASH_BASE     EQU     0x10400000

; External Memory Base Addresses
SMC0_BASE       EQU     0x20000000      ; Static  Memory Bank 0
SMC1_BASE       EQU     0x24000000      ; Static  Memory Bank 1
SMC2_BASE       EQU     0x28000000      ; Static  Memory Bank 2
DYN0_BASE       EQU     0x30000000      ; Dynamic Memory Bank 0


;----------------------- Stack and Heap Definitions ----------------------------

;// <h> Stack and Heap Settings
;//   <h> Stack Configuration (Stack Sizes in Bytes)
;//     <o0> Undefined Mode      <0x0-0xFFFFFFFF:8>
;//     <o1> Supervisor Mode     <0x0-0xFFFFFFFF:8>
;//     <o2> Abort Mode          <0x0-0xFFFFFFFF:8>
;//     <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;//     <o4> Interrupt Mode      <0x0-0xFFFFFFFF:8>
;//     <o5> User/System Mode    <0x0-0xFFFFFFFF:8>
;//   </h>
;//   <h> Heap Configuration
;//     <o6> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;//   </h>
;// </h>

UND_Stack_Size  EQU     0x00000000
SVC_Stack_Size  EQU     0x00000020
ABT_Stack_Size  EQU     0x00000000
FIQ_Stack_Size  EQU     0x00000000
IRQ_Stack_Size  EQU     0x00000080
USR_Stack_Size  EQU     0x00000400
Heap_Size       EQU     0x00000000


; Stack
Stack_Size      EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
                         FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size)

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size

Stack_Top       EQU     Stack_Mem + Stack_Size


; Heap
                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem        SPACE   Heap_Size


;----------------------- System Control Definitions ----------------------------

; System Control User Interface
SYSTEM_BASE     EQU     0x80005000      ; System Control          Base Address
SYS_BOOTMAP_OFS EQU     0x70            ; Boot Map Control
SYS_BOOTADDR_OFS EQU    0x74            ; Boot Address Control
SYS_PARTID_OFS  EQU     0x7C            ; Part Identification


;----------------------- Clock Definitions -------------------------------------

; Clock User Interface
CGU_BASE         EQU    0x80004C00      ; Clock Generation Unit   Base Address
                                        ; Low Power PLL
LPFIN_OFS        EQU    0xE4            ; Input Select
LPPDN_OFS        EQU    0xE8            ; Power Down
LPMBYP_OFS       EQU    0xEC            ; Multiplier Bypass
LPLOCK_OFS       EQU    0xF0            ; Lock Status
LPDBYP_OFS       EQU    0xF4            ; Divisor Bypass
LPMSEL_OFS       EQU    0xF8            ; Multiplication Factor
LPPSEL_OFS       EQU    0xFC            ; Division Factor
                                        ; High Speed PLL
HPFIN_OFS        EQU    0xAC            ; Input Select
HPNDEC_OFS       EQU    0xB4            ; Initial Divider Control
HPMDEC_OFS       EQU    0xB0            ; Multiplier Control
HPPDEC_OFS       EQU    0xB8            ; Final Divider Control
HPMODE_OFS       EQU    0xBC            ; Mode
HPSTAT_OFS       EQU    0xC0            ; Status
HPREQ_OFS        EQU    0xC8            ; Rate Change Request
HPACK_OFS        EQU    0xC4            ; Rate Change Acknowledge
HPSELR_OFS       EQU    0xD8            ; R Bandwidth
HPSELI_OFS       EQU    0xDC            ; I Bandwidth
HPSELP_OFS       EQU    0xE0            ; P Bandwidth

CGUSWBOX_BASE    EQU    0x80004000      ; Clk Gen Unit Switchbox  Base Address
SYSSCR_OFS       EQU    0x00
APB0SCR_OFS      EQU    0x04
APB1SCR_OFS      EQU    0x08
APB3SCR_OFS      EQU    0x0C
DCDCSCR_OFS      EQU    0x10
RTCSCR_OFS       EQU    0x14
MCISCR_OFS       EQU    0x18
UARTSCR_OFS      EQU    0x1C
DAIOSCR_OFS      EQU    0x20
DAISCR_OFS       EQU    0x24
SYSFSR2_OFS      EQU    0x58            
APB0FSR2_OFS     EQU    0x5C
APB1FSR2_OFS     EQU    0x60
APB3FSR2_OFS     EQU    0x64
DCDCFSR2_OFS     EQU    0x68
RTCFSR2_OFS      EQU    0x6C
MCIFSR2_OFS      EQU    0x70
UARTFSR2_OFS     EQU    0x74
DAIOFSR2_OFS     EQU    0x78
DAIFSR2_OFS      EQU    0x7C


; Constants
HPMODE_FR        EQU    (1<<5)          ; High Speed PLL Free run mode selection bit

LPLOCK_ON        EQU    1               ; Low Power PLL lock bit
HPLOCK_ON        EQU    1               ; High Speed PLL lock bit
FREERUN_ON       EQU    (1<<1)          ; Free Running active bit

;// <e> Clock Configuration
CLOCK_SETUP      EQU    1

;//   <e> Use Low Power PLL
;//     <o1.0..2> LPFIN: Input Select Register
;//                     <0=> 32 kHz oscillator
;//                     <1=> Fast (12 MHz) oscillator
;//                     <2=> MCLKI pin
;//                     <3=> BCKI pin
;//                     <4=> WSI pin
;//                     <7=> High Speed PLL
;//     <o2.0> LPMBYP: Multiplier Bypass Register
;//     <o3.0> LPDBYP: Divisor Bypass Register
;//     <o4.0..4> LPMSEL: Multiplication Factor <0-15>
;//       <i> If LPMBYP = 0 then calculate LPMSEL to get desired Fclkout
;//       <i> by using following formula Fclkout = Fclkin * (LPMSEL + 1)
;//     <o5.0..4> LPPSEL: Division Factor <0-15>
;//       <i> If LPDBYP = 0 then calculate LPPSEL to satisfy following 
;//       <i> condition 160 MHz <= Fclkout * 2^(LPPSEL+1) <= 320 MHz
;//   </e>
LPPLL_SETUP      EQU    1
LPFIN_Val        EQU    0x00000001
LPMBYP_Val       EQU    0x00000000
LPDBYP_Val       EQU    0x00000000
LPMSEL_Val       EQU    0x00000004
LPPSEL_Val       EQU    0x00000001

;//   <h> Selection Stage Setting
;//     <h> Frequency Select 2 Registers
;//       <o0.0..3> SYSFSR2: Side 2 SYS Clock Selection
;//                     <0=> 32 kHz oscillator <1=> Fast oscillator <2=> MCI Clock pin
;//                     <3=> DAI BCLK pin      <4=> DAI WS pin      <7=> High Speed PLL
;//                     <8=> Main PLL
;//       <o1.0..3> APB0FSR2: Side 2 APB0 Clock Selection
;//                     <0=> 32 kHz oscillator <1=> Fast oscillator <2=> MCI Clock pin
;//                     <3=> DAI BCLK pin      <4=> DAI WS pin      <7=> High Speed PLL
;//                     <8=> Main PLL
;//       <o2.0..3> APB1FSR2: Side 2 APB1 Clock Selection
;//                     <0=> 32 kHz oscillator <1=> Fast oscillator <2=> MCI Clock pin
;//                     <3=> DAI BCLK pin      <4=> DAI WS pin      <7=> High Speed PLL
;//                     <8=> Main PLL
;//       <o3.0..3> APB3FSR2: Side 2 APB3 Clock Selection
;//                     <0=> 32 kHz oscillator <1=> Fast oscillator <2=> MCI Clock pin
;//                     <3=> DAI BCLK pin      <4=> DAI WS pin      <7=> High Speed PLL
;//                     <8=> Main PLL
;//       <o4.0..3> DCDCFSR2: Side 2 DCDC Clock Selection
;//                     <0=> 32 kHz oscillator <1=> Fast oscillator <2=> MCI Clock pin
;//                     <3=> DAI BCLK pin      <4=> DAI WS pin      <7=> High Speed PLL
;//                     <8=> Main PLL
;//       <o5.0..3> RTCFSR2: Side 2 RTC Clock Selection
;//                     <0=> 32 kHz oscillator <1=> Fast oscillator <2=> MCI Clock pin
;//                     <3=> DAI BCLK pin      <4=> DAI WS pin      <7=> High Speed PLL
;//                     <8=> Main PLL
;//       <o6.0..3> MCIFSR2: Side 2 MCI Clock Selection
;//                     <0=> 32 kHz oscillator <1=> Fast oscillator <2=> MCI Clock pin
;//                     <3=> DAI BCLK pin      <4=> DAI WS pin      <7=> High Speed PLL
;//                     <8=> Main PLL