/*****************************************************************************
 *   ex_sdram.c:  External SDRAM memory module file for NXP LPC2xxx Family 
 *   Microprocessors
 *
 *   Copyright(C) 2006, NXP Semiconductor
 *   All rights reserved.
 *
 *   History
 *   2007.01.13  ver 1.00    Prelimnary version, first Release
 *
******************************************************************************/
#include "LPC288x.h"				/* LPC2xxx definitions */
#include "type.h"
#include "irq.h"
#include "target.h"
#include "timer.h"
#include "ex_sdram.h"

/*****************************************************************************
** Function name:		delayMs
**
** Descriptions:		Start the timer delay in milo seconds
**						until elapsed
**
** parameters:			Delay value in milo second			 
** 						
** Returned value:		None
** 
*****************************************************************************/
void delayMs(DWORD delayInMs)
{
  /*
  * setup timer #1 for delay
  */
  T1LOAD = delayInMs * TIMER_10MS;
  T1CTRL=0xC0;
  
  /* wait until delay time has elapsed */
  while (T1VALUE);
  return;
}

/*****************************************************************************
** Function name:		SDRAMInit
**
** Descriptions:		Initialize external SDRAM memory Samsung 
**						K4S561632H, 256Mbit(4M x 16 bit). The same
**						code can be used for the Micron's MT48LC16M 
** 						For more info. regarding the details of the 
**						SDRAMs, go to their website for data sheet.  
**
** parameters:			None			 
** 						
** Returned value:		None
** 
*****************************************************************************/
void SDRAMInit( void )
{
  DWORD i, dummy = dummy;

  /*************************************************************************
  * Initialize EMC and SDRAM
  *************************************************************************/ 
  EMC_CTRL = 0x00000001;		/*Enable MPMC, Disable Addr mirror */
  EMC_CONFIG = 0x00000000;
  
  EMC_DYN_RP     = 1;		/* command period: 2(n+1) clock cycles */
  EMC_DYN_RAS    = 2;		/* RAS command period: 3(n+1) clock cycles */
  EMC_DYN_SREX   = 4;		/* Self-refresh period: 5(n+1) clock cycles */
  EMC_DYN_APR    = 0;		/* Data out to active: 1(n+1) clock cycles */
  EMC_DYN_DAL    = 4;		/* Data in to active: 5(n+1) clock cycles */
  EMC_DYN_WR     = 1;		/* Write recovery: 2(n+1) clock cycles */
  EMC_DYN_RC     = 4;		/* Active to Active cmd: 5(n+1) clock cycles */
  EMC_DYN_RFC    = 4;		/* Auto-refresh: 5(n+1) clock cycles */
  EMC_DYN_XSR    = 4;		/* Exit self-refresh: 5(n+1) clock cycles */
  EMC_DYN_RRD    = 1;		/* Active bank A->B: 2(n+1) clock cycles */
  EMC_DYN_MRD    = 1;		/* Load Mode to Active cmd: 2(n+1) clock cycles */

  EMC_DYN_RD_CFG = 1;		/* Command delayed strategy */

  /* Default setting, RAS latency 2 CCLKs, CAS latenty 2 CCLKs. */
  EMC_DYN_RASCAS0 = 0x00000202;

  /* low-power SDRAM, 8Mx16, 4 banks, row=12, column=9 */
  EMC_DYN_CFG0 = 0x00001488;
  delayMs(10);

  /* Mem clock enable, CLKOUT runs, send command: NOP */
  EMC_DYN_CTRL = 0x00000183;
  delayMs(20);
    
  /* Send command: PRECHARGE-ALL, shortest possible refresh period */
  EMC_DYN_CTRL = 0x00000103;

  /* set 32 CCLKs between SDRAM refresh cycles */
  EMC_DYN_RFSH = 0x00000002;
  for(i = 0; i < 0x40; i++);	/* wait 128 AHB clock cycles */
    
  /* set 28 x 16CCLKs=448CCLK=7us between SDRAM refresh cycles */
  EMC_DYN_RFSH = 0x1C;
    
  /* To set mode register in SDRAM, enter mode by issue
  MODE command, after finishing, bailout and back to NORMAL mode. */    
  /* Mem clock enable, CLKOUT runs, send command: MODE */
  EMC_DYN_CTRL = 0x00000083;
  
  /* Set mode register in SDRAM */
  /* Please note, this is a BRC part, shift = # of columns + N
  where N=0 for 8 bit, N=1 for 16 bits, and N=2 for 32 bits.
  for RBC part, shift = # of column + # of banks + N, where 
  N=0 for 8 bit, N=1 for 16 bits, and N=2 for 32 bits. */ 
  /* Mode regitster table for Micron's MT48LCxx */
  /* bit 9:   Programmed burst length(0)
     bit 8~7: Normal mode(0)
	 bit 6~4: CAS latency 2
	 bit 3:   Sequential(0)
	 bit 2~0: Burst length is 8
	 row position is 12 */
  dummy = *((volatile DWORD *)(SDRAM_BASE_ADDR | (0x23 << 10)));
  
  EMC_DYN_CTRL = 0x00000000;	  /* Send command: NORMAL */

  EMC_DYN_CFG0 |= 0x00080000;	  /* Enable buffer */
  delayMs(1);
  return;

}

/*********************************************************************************
**                            End Of File
*********************************************************************************/