//heima's 51 defs
#define TRUE 	1
#define FALSE	0

#define HIGH	1
#define LOW		0

#define ENABLE  1
#define DISABLE 0



#define uchar   unsigned char
#define uint    unsigned int
#define ulong   unsigned long
#define byte	unsigned char

sbit P0_0 = P0^0;
sbit P0_1 = P0^1;
sbit P0_2 = P0^2;
sbit P0_3 = P0^3;
sbit P0_4 = P0^4;
sbit P0_5 = P0^5;
sbit P0_6 = P0^6;
sbit P0_7 = P0^7;

sbit P1_0 = P1^0;
sbit P1_1 = P1^1;
sbit P1_2 = P1^2;
sbit P1_3 = P1^3;
sbit P1_4 = P1^4;
sbit P1_5 = P1^5;
sbit P1_6 = P1^6;
sbit P1_7 = P1^7;

sbit P2_0 = P2^0;
sbit P2_1 = P2^1;
sbit P2_2 = P2^2;
sbit P2_3 = P2^3;
sbit P2_4 = P2^4;
sbit P2_5 = P2^5;
sbit P2_6 = P2^6;
sbit P2_7 = P2^7;

sbit P3_0 = P3^0;
sbit P3_1 = P3^1;
sbit P3_2 = P3^2;
sbit P3_3 = P3^3;
sbit P3_4 = P3^4;
sbit P3_5 = P3^5;
sbit P3_6 = P3^6;
sbit P3_7 = P3^7; 


sfr   IPH =0xB7	;
sbit  EPCA_LVD= IE^6 ;
sfr   CH = 0xF9		  ;//HIGHT 8 OF PCA COUNTER 
sfr   CL = 0xE9;		 	 

sfr   CCON = 0xD8 ;
sbit  CCF0 = CCON^0;
sbit  CCF1 = CCON^1;
sbit  CCF2 = CCON^2;
sbit  CCF3 = CCON^3;
sbit  CCF4 = CCON^4;
sbit  CCF5 = CCON^5;
sbit  CR =	 CCON^6;
sbit  CF =	 CCON^7;

sfr  CMOD= 	0xD9 ;
//CMOD.7    CIDL    0 COUNT WHEN THE CPU IS IDLE
//CMOD.2    CPS1
//CMOD.1	CPS0
//00-->  FOSC/12
//01-->  FOSC/2
//10-->  TIMER0 
//11-->	 ECI/P3.4
//CMOD.0	ECF

sfr  CCAP0H =   0xFA ;
sfr  CCAP1H =   0xFB ;
			
sfr  CCAP0L =   0xEA  ;
sfr  CCAP1L =   0xEB ;

sfr  PCA_PWM0 = 0xF2  ;
sfr  PCA_PWM1 = 0xF3 ;

sfr  CCAPM0 =   0xDA  ;
sfr  CCAPM1 =   0xDB ;