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<html><head> <title>Operating Systems FAQ :: Acronyms</title> <link rel=stylesheet type="text/css" href="default.css"></head><body><P> </P><TABLE border="0" width="100%"> <TR> <TD><H2><A name="acronyms">Chip Numbers, Acronyms and Things</A></H2> </TD> </TR> <TR> <TD><STRONG>6845</STRONG><BR>Graphics controller chip used in many many graphic adaptors<P><STRONG>8042</STRONG><BR>Controller chip in the AT keyboard</P><P><STRONG>8048</STRONG><BR>Controller chip in the XT keyboard</P><P><STRONG>82072A</STRONG><BR>Controller chip in the AT floppy disk drive</P><P><STRONG>82077A</STRONG><BR>Controller chip in PS2 floppy disk drive. Successor to the 82072A</P><P><STRONG>82284</STRONG><BR>The 80286 clock generator</P><P><STRONG>82288</STRONG><BR>The 80286 bus controller chip</P><P><STRONG>8237A</STRONG><BR>An 8bit DMA controller in the XT. Two chips in the AT and beyond, with four DMA channels per chip. Chips can be cascaded.</P><P><STRONG>82450</STRONG><BR>UART chip in the AT, successor to the 8250.</P><P><STRONG>82489DX</STRONG><BR>Advanced Programmable Interrupt Controller (APIC) in Pentiums and multiprocessor systems. The successor to the 8259A PIC.</P><P><STRONG>8253</STRONG><BR>Programmable Interval Timer (PIT) chip in the XT and AT. Has three independent timers.</P><P><STRONG>8254</STRONG><BR>Programmable Interval Timer (PIT). Used in AT's and EISA/MCA machines. Just an improved version of the 8253.</P><P><STRONG>8259A</STRONG><BR>Programmable Interrupt Controller (PIC) used in all PC's that predate Pentiums (Even many Pentiums and clones still use this instead of the APIC). Each chip has 8 interrupt lines. AT and beyond have two chips.</P><P><STRONG>8284</STRONG><BR>Clock generator in the 8088/8086/80186</P><P><STRONG>8288</STRONG><BR>Bus controller in the 8088/8086/80186</P><P><STRONG>8741</STRONG><BR>Common controller chip in AT keyboards</P><P><STRONG>8742</STRONG><BR>Controller chip in PS2 keyboards</P><P><STRONG>ABIOS</STRONG><BR>Advanced BIOS. Refers to BIOS that support BIOS calls in Protected Mode.</P><P><STRONG>ARLL</STRONG><BR>Advanced RLL. Method used in Hard Disks. MFM, RLL, etc.</P><P><STRONG>ASPI</STRONG><BR>Advanced SCSI Programming Interface. An ADAPTEC thing, its a common interface for programming SCSI devices.</P><P><STRONG>ATA</STRONG><BR>AT Attachment. Basically an IDE device (hd, cdrom, etc). Standards for connecting Hard Disks to an AT bus.</P><P><STRONG>BIST</STRONG><BR>Built In Self Test.</P><P><STRONG>Booting</STRONG><BR>The loading of the BIOS and kicking in the bootsector to bootstrap an OS loader.</P><P><STRONG>Bootstrap</STRONG><BR>The bootstrap is a small program that loads an operating system. (Usually synonymous with the bootsector/MBR).</P><P><STRONG>Bus Master</STRONG><BR>Where a device can control the BUS autonomously. Examples of this are the CPU and DMA chips.Other controller chips can also do this (ala some PCI devices, etc).</P><P><STRONG>Call Gate</STRONG><BR>Much like an software driven interrupt, a call gate allows access to other code from a different privilege level.</P><P><STRONG>Combicontroller</STRONG><BR>Combine a Floppy disk controller chip and a Hard disk controller chip and you have a combicontroller.It is not limited to just floppy+hard drive chips.Usually meant to refer to the actual plug-in card where you have two floppy and two hd IDE ports.</P><P><STRONG>Descriptor</STRONG><BR>An 8 byte structure that describes a segment/gate/task in protected mode.</P><P><STRONG>DMA</STRONG><BR>Direct Memory Access. Allows peripheral devices to access main memory directly, bypassing the CPU.</P><P><STRONG>EISA</STRONG><BR>Extended ISA. Basically extends the ISA bus from being 8bit to being 32bit. Designed for 386 + 486 systems.</P><P><STRONG>ESDI</STRONG><BR>Enhanced Small Device Interface. A hard disk controlling mechanism. Successor to the ST506/412 interface. Can handle pumping data out at 24mbits (3mb a second)</P><P><STRONG>Exception</STRONG><BR>CPU error. Usually hardware triggered, but can also be software triggered (some debug breakpoints, etc)</P><P><STRONG>Expanded Memory</STRONG><BR>Memory used by an EMS driver. Located beyond 1mb mark.</P><P><STRONG>Extended Memory</STRONG><BR>Memory used by an XMS driver. Located beyond the 1mb mark. The first 64kb of XMS is known as HMA (High Memory Area).</P><P><STRONG>Fault</STRONG><BR>An exception that is recognised by the processor before the CPU executes the code. eg: trying to access memory swapped out to disk triggers a fault BEFORE the memory is accessed so it can be swapped into memory.</P><P><STRONG>FDC</STRONG><BR>Floppy Disk Controller</P><P><STRONG>FIFO</STRONG><BR>First In First Out. FIFO buffers are common in newer UART chips for communications (16550AFN)</P><P><STRONG>GDT</STRONG><BR>Global Descriptor Table. This table contains descriptors that are potentially available to all programs in protected mode.</P><P><STRONG>HAL<BR></STRONG>Hardware Abstraction Layer. Used by WindowsNT and some other operating systems. Lets NT "emulate" or "pretend" certain hardware exists even if not in your system.</P><P><STRONG>HDC</STRONG><BR>Hard Disk Controller</P><P><STRONG>IDE</STRONG><BR>Intelligent Drive Electronics. A standard for connecting hard disks, floppies, etc. to the AT bus.</P><P><STRONG>IDT</STRONG><BR>Interrupt Descriptor Table. Table of 8byte entries that describe interrupts, traps, exceptions and fault handlers to the CPU.</P><P><STRONG>Interrupt</STRONG><BR>Interrupts can be software or hardware generated. When an interrupt occurs, the CPU jumps to code assigned to be ran whenever that interrupt is triggered.</P><P><STRONG>Interrupt Gate</STRONG><BR>A descriptor for calling an interrupt.</P><P><STRONG>IRQ</STRONG><BR>Interrupt Request. Hardware signal to the CPU from an external peripheral.</P><P><STRONG>ISA</STRONG><BR>Industry Standard Architecture. The defined BUS standard for AT's.</P><P><STRONG>LDT</STRONG><BR>Local Descriptor Table. A table of descriptors that can only be accessed by the task that owns the LDT and none other.</P><P><STRONG>MC146818</STRONG><BR>CMOS ram and Real Time Clock chip in the AT.</P><P><STRONG>MMU</STRONG><BR>Memory Management Unit. The MMU is often contained within the CPU but can be external to the CPU. eg: old 68k CPU's did not have an MMU but one could be attached externally. The MMU is responsible for doing things like address segmentation translation and paging.</P><P><STRONG>PD765</STRONG><BR>The floppy controller chip in the XT</P><P><STRONG>Multitasking</STRONG><BR>Where the CPU 'appears' to be running several tasks all at the same time.</P><P><STRONG>Multitasking OS</STRONG><BR>The difference between unix and dos :> joke! see Multitasking. good examples of MOS and nonMOS are unix to dos, vms to cpm, etc.</P><P><STRONG>Nibble</STRONG><BR>Group of 4 bits. Half a byte... Quarter a word... Eith of a dword... etc..</P><P><STRONG>NMI</STRONG><BR>Non Maskable Interrupt. An interrupt request sent to the CPU that must be dealt with immediately.</P><P><STRONG>Page</STRONG><BR>Section of memory that is classed as a single entity. eg: x86 in pmode has pages of 1byte, 4kb and 4mb in size.</P><P><STRONG>Page Directory</STRONG><BR>Holds the entries for the paging table mechanism. Unlike Page Tables, the Page Directory can't be swapped out of memory.</P><P><STRONG>PCI</STRONG><BR>Peipheral Component Interconnect. A Local Bus standard running at 32bits at 33mhz (can go higher). PCI has replaced ISA as the most common bus interface for desktopish computers.</P><P><STRONG>PCMCIA</STRONG><BR>Personal Computer Memory Card International Association. Small credit card sized units that plug into portable computer PCMCIA slot and provide things like extra memory, modems, etc.</P><P><STRONG>PIC</STRONG><BR>Programmable Interrupt Controller. The PIC manages hardware interrupts.</P><P><STRONG>PIT</STRONG><BR>Programmable Interval Timer. The PIT is like a stopwatch with periodic alarm...</P><P><STRONG>POST</STRONG><BR>Power On Self Test. Your computer does this when you turn it on in order to assess that its 100% A-OK and can boot up without error.</P><P><STRONG>RTC</STRONG><BR>Real Time Clock</P><P><STRONG>SCSI</STRONG><BR>Small Computer Systems Interface. A different method from ATA/IDE for connecting devices to your computer.</P><P><STRONG>Selector</STRONG><BR>An index into a descriptor table.</P><P><STRONG>ST506/412</STRONG><BR>Physical interface between a hard disk and computer.</P><P><STRONG>Task</STRONG><BR>AKA a process or job. A task is just another program.</P><P><STRONG>Task Switch</STRONG><BR>Changing from one task to another in an multi-tasking operating system.</P><P><STRONG>Trap</STRONG><BR>An exception which occurs AFTER the error has occurred instead of before (see Fault).</P><P><STRONG>TSS</STRONG><BR>Task State Segment. A data structure that holds the state of the CPU when for that task. Used by multitasking OS.</P><P><STRONG>Vesa Local Bus (VLB)</STRONG><BR>BUS system for 386 and 486 machines. CPU speed specific.</P> </TD> </TR></TABLE></body></html>?? 快捷鍵說明
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