lis	r5, HIADJ(0x00600000)   /* See docs for detail description of SIUMcR */	addi	r5, r5, LO(0x00600000) /* See docs for detail description of SIUMCR */	stw	r5, SIUMCR(0)(r4)	divw	r5, r4, r4		/* waste time (r4 != 0) */	divw	r5, r4, r5		/* 13 clocks		*/	nop	nop	isync		/* 	 * we program the MPTPR with the largest allowed divider 	 * and the PTA value accordingly. So here we figure out the 	 * correct value for the PTA field.	 */	li	r6, MPTPR_PTP_DIV64         lis     r11, HIADJ ((REFRESH_VALUE / 64) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 64) << MAMR_PTA_SHIFT)        cmpwi   r11,0        bne     mptprInit	/* try with the divider by 32 */	li	r6, MPTPR_PTP_DIV32         lis     r11, HIADJ ((REFRESH_VALUE / 32) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 32) << MAMR_PTA_SHIFT)        cmpwi   r11,0        bne     mptprInit	/* try with the divider by 16 */	li	r6, MPTPR_PTP_DIV16         lis     r11, HIADJ ((REFRESH_VALUE / 16) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 16) << MAMR_PTA_SHIFT)        cmpwi   r11,0        bne     mptprInit	/* try with the divider by 8 */	li	r6, MPTPR_PTP_DIV8         lis     r11, HIADJ ((REFRESH_VALUE / 8) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 8) << MAMR_PTA_SHIFT)        cmpwi   r11,0        bne     mptprInit	/* try with the divider by 4 */	li	r6, MPTPR_PTP_DIV4         lis     r11, HIADJ ((REFRESH_VALUE / 4) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 4) << MAMR_PTA_SHIFT)        cmpwi   r11,0        bne     mptprInit	/* it has to be the divide by 2 */	li	r6, MPTPR_PTP_DIV2         lis     r11, HIADJ ((REFRESH_VALUE / 2) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 2) << MAMR_PTA_SHIFT)mptprInit:	/* program the MPTPR */	sth	r6, MPTPR(0)(r4)         /* 	 * initialize MxMR but don't enable refresh until after 	 * SDRAM initialization.         */        lis     r6, HIADJ (MAMR_DEFAULT_VALUE)        addi    r6, r6, LO (MAMR_DEFAULT_VALUE)        or      r6, r6, r11                              stw     r6, MAMR(0)(r4)        lis     r6, HIADJ (MBMR_DEFAULT_VALUE)        addi    r6, r6, LO (MBMR_DEFAULT_VALUE)        or      r6, r6, r11                             stw     r6, MBMR(0)(r4)        /*         * load r6/r7 with the start/end address of the UPM table for an         * SDRAM @ 50MHZ.         */        lis     r6, HIADJ( upmbTableSdram)        addi    r6, r6, LO(upmbTableSdram)        lis     r7, HIADJ( upmbTableSdramEnd)        addi    r7, r7, LO(upmbTableSdramEnd)         /* init UPMB for memory access */         sub     r5, r7, r6              /* compute table size */        srawi   r5, r5, 2               /* in integer size */         /* convert UpmTable to ROM based addressing */         lis     r7, HIADJ(romInit)        addi    r7, r7, LO(romInit)         lis     r8, HIADJ(ROM_TEXT_ADRS)        addi    r8, r8, LO(ROM_TEXT_ADRS)         sub     r6, r6, r7              /* subtract romInit base address */        add     r6, r6, r8              /* add in ROM_TEXT_ADRS address */         lis     r9, HIADJ (MCR_OP_WRITE | MCR_UM_UPMB | MCR_MB_CS0)        addi    r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMB | MCR_MB_CS0) UpmbWriteLoop:        /* write the UPM table in the UPM */         lwz     r10, 0(r6)              /* get data from table */        stw     r10, MDR(0)(r4)         /* store the data to MD register */         stw     r9, MCR(0)(r4)          /* issue command to MCR register */         addi    r6, r6, 4               /* next entry in the table */        addi    r9, r9, 1               /* next MAD address */        addi    r5,r5,-1        cmpwi   r5,0        bne     UpmbWriteLoop        /*          * Issue precharge command (PRCG) and wait the precharge time (t-rp).	 * Run precharge pattern from UPMB location 5.         */        lis     r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \			  MCR_MCLF_1X | 0x5)        addi    r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \			   MCR_MCLF_1X | 0x5)        stw     r5, MCR(0)(r4)         /* run refresh pattern 8 times */        lis     r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \			  MCR_MCLF_8X | 0x30)        addi    r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \			  MCR_MCLF_8X | 0x30)        stw     r5, MCR(0)(r4)         /* 	 * Configure the 32 bit address to be output on the address bus 	 * if AMX = 0xb11.         * See section 16.6.4.1 "Arm Words".  The following values must 	 * be placed on the defined SDRAM address pins:         *   A[9]   = 0          burst write mode         *   A[6:4] = 010        cas latency of two         *   A[3]   = 0          sequential mode         *   A[2:0] = 010        burst length 4         *         * The address must be shifted left by 2 bits for 32 bit wide SDRAM...         *   (0b0100010 << 2) = 0x88         */        lis     r5, HIADJ(LOCAL_MEM_LOCAL_ADRS | 0x88)        addi    r5, r5, LO(LOCAL_MEM_LOCAL_ADRS | 0x88)        stw     r5, MAR(0)(r4)         /* 	 * issue a mode register set (MRS) to initialize the SDRAM mode 	 * register.  This programs the burst length, CAS latency and 	 * write mode. Run MRS pattern from UPMB location 6.         */        lis     r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \			  MCR_MCLF_1X | 0x6)        addi    r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \			  MCR_MCLF_1X | 0x6)        stw     r5, MCR(0)(r4)	/* program OR4 and BR4 for 4 Mbytes SDRAM Memory Array */	lis	r5, HIADJ  ((~(SDRAM_SIZE - 1)) | OR_CSNT_SAM)	addi    r5, r5, LO ((~(SDRAM_SIZE - 1)) | OR_CSNT_SAM)	stw	r5, OR4(0)(r4)	/* set OR4 to the previously computed value */	lis	r5, HIADJ ((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMB \			    | BR_V)	addi    r5, r5, LO ((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMB \			    | BR_V)	stw	r5, BR4(0)(r4)		/* program OR/BR5 for BCSR50 */	lis	r5, HIADJ  (0xffff8110)       /* Minimun wait states */	addi    r5, r5, LO (0xffff8110)       /* Minimun wait states */	stw	r5, OR5(0)(r4)	/* set OR4 to the previously computed value */	lis	r5, HIADJ (0x2000000 | BR_V)  /* 32 bit port and valid*/	addi    r5, r5, LO (0x2000000 | BR_V)	stw	r5, BR5(0)(r4)	/* enable SDRAM refresh cycles */        lis     r5, HIADJ (MBMR_DEFAULT_VALUE | MAMR_PTBE)        addi    r5, r5,LO (MBMR_DEFAULT_VALUE | MAMR_PTBE)	add	r5, r5, r11        stw     r5, MBMR(0)(r4)        /* disable all devices (serial, ethernet, ...) */	lis	r4, HI(BCSR0_RESET_VAL)	lis	r5, HIADJ (BCSR0)	stw	r4, LO(BCSR0)(r5)		/* reset the BCSR0 register */	lis	r4, HI(BCSR1_RESET_VAL)	lis	r5, HIADJ (BCSR1)	stw	r4, LO(BCSR1)(r5)		/* reset the BCSR1 register */	lis	r4, HI(BCSR2_RESET_VAL)	lis	r5, HIADJ (BCSR2)	stw	r4, LO(BCSR2)(r5)		/* reset the BCSR2 register */	lis	r4, HI(BCSR3_RESET_VAL)	lis	r5, HIADJ (BCSR3)	stw	r4, LO(BCSR3)(r5)		/* reset the BCSR3 register */	lis	r4, HI(BCSR4_RESET_VAL)	lis	r5, HIADJ (BCSR4)	stw	r4, LO(BCSR4)(r5)		/* reset the BCSR4 register */ 	li	r4, BCSR5_RESET_VAL	lis	r5, HIADJ (BCSR5)	stb	r4, LO(BCSR5)(r5)		/* reset the BCSR5 register */ 	        /* initialize the stack pointer */	lis	sp, HIADJ(STACK_ADRS)	addi	sp, sp, LO(STACK_ADRS)	        /* initialize r2 and r13 according to EABI standard */#if	FALSE					/* SDA Not supported yet */	lis	r2, HIADJ(_SDA2_BASE_)	addi	r2, r2, LO(_SDA2_BASE_)	lis	r13, HIADJ(_SDA_BASE_)	addi	r13, r13, LO(_SDA_BASE_)#endif	/* go to C entry point */	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */	/* 	 * calculate C entry point: routine - entry point + ROM base 	 * routine	= romStart	 * entry point	= romInit	= R7	 * ROM base	= ROM_TEXT_ADRS = R8	 * C entry point: romStart - R7 + R8 	 */        lis	r6, HIADJ(romStart)	        addi	r6, r6, LO(romStart)	/* load R6 with C entry point */	sub	r6, r6, r7		/* routine - entry point */	add	r6, r6, r8 		/* + ROM base */	mtlr	r6			/* move C entry point to LR */	blr				/* jump to the C entry point */FUNC_END(_romInit)FUNC_END(romInit)/* This SDRAM table is for 885 on DUET. It is detailed in ADS885 DUET UM */ upmbTableSdram: /* single read   (offset 0x00 in upm ram) */       .long   0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00       .long   0x1ff77c47, 0x1ff77c34, 0xefeabc34, 0x1fb57c35/* burst read    (offset 0x08 in upm ram) */       .long   0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00       .long   0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04/* single write  (offset 0x18 in upm ram) */       .long   0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04/* burst write   (offset 0x20 in upm ram) */       .long   0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00       .long   0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xfffffc04       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04/* refresh       (offset 0x30 in upm ram) */       .long   0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04       .long   0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04/* exception     (offset 0x3C in upm ram) */       .long   0x7ffffc07, 0xfffffc04, 0xfffffc04, 0xfffffc04 upmbTableSdramEnd: