library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity h_m_s is
port(clks,clk0,clk: in std_logic;
     lock: in std_logic_vector(2 downto 0);
     clkd: out std_logic;
sh,sl,mh,ml,hh,hl,clkm,clkh: buffer std_logic_vector(3 downto 0));
end h_m_s;
architecture hms of h_m_s is
begin
process(lock,clk1,clks,clkm,clkh)
begin                     
if (lock=”000”)then
clks<=clk;
elsif (lock=”110”)then
  clks<=clk0;
elsif (lock=”101”)then  
  clkm<=clk0;
elsif (lock=”100”)then
  clkh<=clk0;
end if;
--以上為時鐘定義

process(lock,clk1,clks,clkm,clkh)           
if(clks’=’1’ and clks’ event)then
  if(sh=”0101” and sl=”1001”)then
    sh<=”0000”,sl<=”0000”,clkm<=’1’;
elsif(sl=”1001”)then
    sh<=sh+’1’,sl<=”0000”;
else sl<=sl+’1’,clkm<=’0’;
  end if;
end if;
--以上為秒定義

process(lock,clk1,clks,clkm,clkh)          
if(clkm’=’1’ and clkm’ event)then
  if(mh=”0101” and ml=”1001”)then
mh<=”0000”,ml<=”0000”,clkh<=’1’;
  elsif(ml=”1001”)then
mh<=mh+’1’,ml<=”0000”;
  else sl<=sl+’1’,clkh<=’0’;
  end if;
end if;
--以上為分定義

process(lock,clk1,clks,clkm,clkh)              
if(clkh’=’1’ and clkh’ event)then
  if(hh=”0010” and hl=”0011”)then
hh<=”0000”,hl<=”0000”,clkd<=’1’;
  elsif(hl=”1001”)then
hh<=hh+’1’,hl<=”0000”;
  else hl<=hl+’1’,clkd<=’0’;
  end if;
end if;
end process;
end hms;
--以上為小時定義

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity y_m_d is
port(clkd,clk0,clk: in std_logic;
    lock: in std_logic_vector(2 downto 0);
    clky: out std_logic;
dh,dl,monh,monl,yh,yl,clkmon: buffer std_logic_vector(3 downto 0));
end y_m_d;
architecture ymd of y_m_d is        
begin
process(clk0,clkd,clky)                
begin
if lock=”000” then
  clkd<=clk;
elsif lock=”011” then
  clkd<=clk0;
elsif lock=”010” then
  clkmon<=clk0;
elsif lock=”001” then
  clky<=clk0;
end if;

process(clk0,clkd,clky)                
if (clk’=’1’ and clk’ event)then
  if (((monh=”0000” and (monl=”0001” or monl=”0011” or monl=”0101” or monl=”0111” or monl=”1000”))or (monh=”0001” and (monl=”0000” or monl=”0010”))) and dh=”0011” and dl=”0001”)then    --大月的31日
    dh<=”0000”,dl<=”0001”,clkmon<=’1’;
  elsif (((monh=”0000” and (monl=”0001” or monl=”0011” or monl=”0101” or monl=”0111” or monl=”1000”))or (monh=”0001” and (monl=”0000” or monl=”0010”))) and dl=”1001”)then     --大月的9,19或29日
    dh<=dh+’1’,dl<=”0001”;
  elsif (((monh=”0000” and (monl=”0100” or monl=”0110” or monl=”1001”))or (monh=”0001” and monl=”0001”))and dh=”0011” and dl=”0000”)then  --小月30日
    dh<=”0000”,dl<=”0001”,clkmon<=’1’;
  elsif (((monh=”0000” and (monl=”0100” or monl=”0110” or monl=”1001”))or (monh=”0001” and monl=”0001”)) and dl=”1001”)then  --小月9,19或29日
    dh<=dh+’1’,dl<=”0001”;
  elsif (yl=”XX00” and monh=”0000” and monl=”0010” and dh=”0010” and dl=”1001”)then   --閏年二月29日
    dh<=”0000”,dl<=”0001”,clkmon<=’1’;
  elsif (yl=”XX00” and monh=”0000” and monl=”0010” and dl=”1001”)then --閏年二月9,19日
    dh<=dh+’1’;,dl<=”0001”;
  elsif (y1/”XX00” and month=”0000” and monl=”0010” and dh=”0010” and dl=”1000”)then             --平年二月28日
    dh<=”0000”,dl<=”0001”,clkmon<=’1’;
  elsif (yl/”XX00” and month=”0000” and monl=”0010” and dl=”1001”)then --平年二月9,19日
    dh<=dh+’1’,dl<=”0001”;
  else dl<=dl+’1’,clkmon<=’0’;
  end if;
end if;
--以上為日期定義

process(clk0,clkd,clky)                    
if (clkmon’=’1’ and clkmon’ event)then
  if (monh=”0001” and monl=”0010”)then
    monh<=”0000”,monl<=”0001”,clky<=’1’;
  elsif (monh=”0000” and monl=”1001”)then
    monh<=monh+’1’,monl<=”0001”;
  else monl<=monl+’1’,clky<=’0’;
  end if;
end if;
--以上為月份定義

process(clk0,clkd,clky)
if (clky’=’1’ and clky’ event)then
  if(yh=”1001” and yl=”1001”)then
    yh<=”0000”,yl<=”0000”;
  elsif(yl=”1001”)then
    yh<=yh+’1’,yl<=”0000”;
  else yl<=yl+’1’;
  end if;
end if;
end process;
end ymd;
--以上為年定義

--以下為時間修改  時鐘計數器定義
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity s_t is
port(clk:in std_logic;
lockut std_logic_vector(2 downto 0);
end s_t;
architecture st of s_t is
begin
process(clk,lock)
begin
if (clk’=’1’ and clk’ event)then
  if (lock=”110”)then
lock<=”000”;
  else lock<=lock+’1’;
  end if;
end if;