<p><pre>AAS                           ; 3F                   [8086]</pre><p><pre>AAD                           ; D5 0A                [8086] AAD imm                       ; D5 ib                [8086]</pre><p><pre>AAM                           ; D4 0A                [8086] AAM imm                       ; D4 ib                [8086]</pre><p>These instructions are used in conjunction with the add, subtract,multiply and divide instructions to perform binary-coded decimal arithmeticin <em>unpacked</em> (one BCD digit per byte - easy to translate to andfrom <code><nobr>ASCII</nobr></code>, hence the instruction names) form.There are also packed BCD instructions <code><nobr>DAA</nobr></code> and<code><nobr>DAS</nobr></code>: see <a href="#section-B.4.57">sectionB.4.57</a>.<ul><li><code><nobr>AAA</nobr></code> (ASCII Adjust After Addition) should beused after a one-byte <code><nobr>ADD</nobr></code> instruction whosedestination was the <code><nobr>AL</nobr></code> register: by means ofexamining the value in the low nibble of <code><nobr>AL</nobr></code> andalso the auxiliary carry flag <code><nobr>AF</nobr></code>, it determineswhether the addition has overflowed, and adjusts it (and sets the carryflag) if so. You can add long BCD strings together by doing<code><nobr>ADD</nobr></code>/<code><nobr>AAA</nobr></code> on the lowdigits, then doing<code><nobr>ADC</nobr></code>/<code><nobr>AAA</nobr></code> on eachsubsequent digit.<li><code><nobr>AAS</nobr></code> (ASCII Adjust AL After Subtraction) workssimilarly to <code><nobr>AAA</nobr></code>, but is for use after<code><nobr>SUB</nobr></code> instructions rather than<code><nobr>ADD</nobr></code>.<li><code><nobr>AAM</nobr></code> (ASCII Adjust AX After Multiply) is foruse after you have multiplied two decimal digits together and left theresult in <code><nobr>AL</nobr></code>: it divides<code><nobr>AL</nobr></code> by ten and stores the quotient in<code><nobr>AH</nobr></code>, leaving the remainder in<code><nobr>AL</nobr></code>. The divisor 10 can be changed by specifyingan operand to the instruction: a particularly handy use of this is<code><nobr>AAM 16</nobr></code>, causing the two nibbles in<code><nobr>AL</nobr></code> to be separated into<code><nobr>AH</nobr></code> and <code><nobr>AL</nobr></code>.<li><code><nobr>AAD</nobr></code> (ASCII Adjust AX Before Division)performs the inverse operation to <code><nobr>AAM</nobr></code>: itmultiplies <code><nobr>AH</nobr></code> by ten, adds it to<code><nobr>AL</nobr></code>, and sets <code><nobr>AH</nobr></code> tozero. Again, the multiplier 10 can be changed.</ul><h4><a name="section-B.4.2">B.4.2 <code><nobr>ADC</nobr></code>: Add with Carry</a></h4><p><pre>ADC r/m8,reg8                 ; 10 /r                [8086] ADC r/m16,reg16               ; o16 11 /r            [8086] ADC r/m32,reg32               ; o32 11 /r            [386]</pre><p><pre>ADC reg8,r/m8                 ; 12 /r                [8086] ADC reg16,r/m16               ; o16 13 /r            [8086] ADC reg32,r/m32               ; o32 13 /r            [386]</pre><p><pre>ADC r/m8,imm8                 ; 80 /2 ib             [8086] ADC r/m16,imm16               ; o16 81 /2 iw         [8086] ADC r/m32,imm32               ; o32 81 /2 id         [386]</pre><p><pre>ADC r/m16,imm8                ; o16 83 /2 ib         [8086] ADC r/m32,imm8                ; o32 83 /2 ib         [386]</pre><p><pre>ADC AL,imm8                   ; 14 ib                [8086] ADC AX,imm16                  ; o16 15 iw            [8086] ADC EAX,imm32                 ; o32 15 id            [386]</pre><p><code><nobr>ADC</nobr></code> performs integer addition: it adds its twooperands together, plus the value of the carry flag, and leaves the resultin its destination (first) operand. The destination operand can be aregister or a memory location. The source operand can be a register, amemory location or an immediate value.<p>The flags are set according to the result of the operation: inparticular, the carry flag is affected and can be used by a subsequent<code><nobr>ADC</nobr></code> instruction.<p>In the forms with an 8-bit immediate second operand and a longer firstoperand, the second operand is considered to be signed, and issign-extended to the length of the first operand. In these cases, the<code><nobr>BYTE</nobr></code> qualifier is necessary to force NASM togenerate this form of the instruction.<p>To add two numbers without also adding the contents of the carry flag,use <code><nobr>ADD</nobr></code> (<a href="#section-B.4.3">sectionB.4.3</a>).<h4><a name="section-B.4.3">B.4.3 <code><nobr>ADD</nobr></code>: Add Integers</a></h4><p><pre>ADD r/m8,reg8                 ; 00 /r                [8086] ADD r/m16,reg16               ; o16 01 /r            [8086] ADD r/m32,reg32               ; o32 01 /r            [386]</pre><p><pre>ADD reg8,r/m8                 ; 02 /r                [8086] ADD reg16,r/m16               ; o16 03 /r            [8086] ADD reg32,r/m32               ; o32 03 /r            [386]</pre><p><pre>ADD r/m8,imm8                 ; 80 /0 ib             [8086] ADD r/m16,imm16               ; o16 81 /0 iw         [8086] ADD r/m32,imm32               ; o32 81 /0 id         [386]</pre><p><pre>ADD r/m16,imm8                ; o16 83 /0 ib         [8086] ADD r/m32,imm8                ; o32 83 /0 ib         [386]</pre><p><pre>ADD AL,imm8                   ; 04 ib                [8086] ADD AX,imm16                  ; o16 05 iw            [8086] ADD EAX,imm32                 ; o32 05 id            [386]</pre><p><code><nobr>ADD</nobr></code> performs integer addition: it adds its twooperands together, and leaves the result in its destination (first)operand. The destination operand can be a register or a memory location.The source operand can be a register, a memory location or an immediatevalue.<p>The flags are set according to the result of the operation: inparticular, the carry flag is affected and can be used by a subsequent<code><nobr>ADC</nobr></code> instruction.<p>In the forms with an 8-bit immediate second operand and a longer firstoperand, the second operand is considered to be signed, and issign-extended to the length of the first operand. In these cases, the<code><nobr>BYTE</nobr></code> qualifier is necessary to force NASM togenerate this form of the instruction.<h4><a name="section-B.4.4">B.4.4 <code><nobr>ADDPD</nobr></code>: ADD Packed Double-Precision FP Values</a></h4><p><pre>ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]</pre><p><code><nobr>ADDPD</nobr></code> performs addition on each of two packeddouble-precision FP value pairs.<p><pre>   dst[0-63]   := dst[0-63]   + src[0-63],    dst[64-127] := dst[64-127] + src[64-127].</pre><p>The destination is an <code><nobr>XMM</nobr></code> register. The sourceoperand can be either an <code><nobr>XMM</nobr></code> register or a128-bit memory location.<h4><a name="section-B.4.5">B.4.5 <code><nobr>ADDPS</nobr></code>: ADD Packed Single-Precision FP Values</a></h4><p><pre>ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]</pre><p><code><nobr>ADDPS</nobr></code> performs addition on each of four packedsingle-precision FP value pairs<p><pre>   dst[0-31]   := dst[0-31]   + src[0-31],    dst[32-63]  := dst[32-63]  + src[32-63],    dst[64-95]  := dst[64-95]  + src[64-95],    dst[96-127] := dst[96-127] + src[96-127].</pre><p>The destination is an <code><nobr>XMM</nobr></code> register. The sourceoperand can be either an <code><nobr>XMM</nobr></code> register or a128-bit memory location.<h4><a name="section-B.4.6">B.4.6 <code><nobr>ADDSD</nobr></code>: ADD Scalar Double-Precision FP Values</a></h4><p><pre>ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]</pre><p><code><nobr>ADDSD</nobr></code> adds the low double-precision FP valuesfrom the source and destination operands and stores the double-precision FPresult in the destination operand.<p><pre>   dst[0-63]   := dst[0-63] + src[0-63],    dst[64-127) remains unchanged.</pre><p>The destination is an <code><nobr>XMM</nobr></code> register. The sourceoperand can be either an <code><nobr>XMM</nobr></code> register or a 64-bitmemory location.<h4><a name="section-B.4.7">B.4.7 <code><nobr>ADDSS</nobr></code>: ADD Scalar Single-Precision FP Values</a></h4><p><pre>ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]</pre><p><code><nobr>ADDSS</nobr></code> adds the low single-precision FP valuesfrom the source and destination operands and stores the single-precision FPresult in the destination operand.<p><pre>   dst[0-31]   := dst[0-31] + src[0-31],    dst[32-127] remains unchanged.</pre><p>The destination is an <code><nobr>XMM</nobr></code> register. The sourceoperand can be either an <code><nobr>XMM</nobr></code> register or a 32-bitmemory location.<h4><a name="section-B.4.8">B.4.8 <code><nobr>AND</nobr></code>: Bitwise AND</a></h4><p><pre>AND r/m8,reg8                 ; 20 /r                [8086] AND r/m16,reg16               ; o16 21 /r            [8086] AND r/m32,reg32               ; o32 21 /r            [386]</pre><p><pre>AND reg8,r/m8                 ; 22 /r                [8086] AND reg16,r/m16               ; o16 23 /r            [8086] AND reg32,r/m32               ; o32 23 /r            [386]</pre><p><pre>AND r/m8,imm8                 ; 80 /4 ib             [8086] AND r/m16,imm16               ; o16 81 /4 iw         [8086] AND r/m32,imm32               ; o32 81 /4 id         [386]</pre><p><pre>AND r/m16,imm8                ; o16 83 /4 ib         [8086] AND r/m32,imm8                ; o32 83 /4 ib         [386]</pre><p><pre>AND AL,imm8                   ; 24 ib                [8086] AND AX,imm16                  ; o16 25 iw            [8086] AND EAX,imm32                 ; o32 25 id            [386]</pre><p><code><nobr>AND</nobr></code> performs a bitwise AND operation betweenits two operands (i.e. each bit of the result is 1 if and only if thecorresponding bits of the two inputs were both 1), and stores the result inthe destination (first) operand. The destination operand can be a registeror a memory location. The source operand can be a register, a memorylocation or an immediate value.<p>In the forms with an 8-bit immediate second operand and a longer firstoperand, the second operand is considered to be signed, and issign-extended to the length of the first operand. In these cases, the<code><nobr>BYTE</nobr></code> qualifier is necessary to force NASM togenerate this form of the instruction.<p>The <code><nobr>MMX</nobr></code> instruction<code><nobr>PAND</nobr></code> (see <a href="#section-B.4.202">sectionB.4.202</a>) performs the same operation on the 64-bit<code><nobr>MMX</nobr></code> registers.<h4><a name="section-B.4.9">B.4.9 <code><nobr>ANDNPD</nobr></code>: Bitwise Logical AND NOT of Packed Double-Precision FP Values</a></h4><p><pre>ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]</pre><p><code><nobr>ANDNPD</nobr></code> inverts the bits of the twodouble-precision floating-point values in the destination register, andthen performs a logical AND between the two double-precision floating-pointvalues in the source operand and the temporary inverted result, storing theresult in the destination register.<p><pre>   dst[0-63]   := src[0-63]   AND NOT dst[0-63],    dst[64-127] := src[64-127] AND NOT dst[64-127].</pre><p>The destination is an <code><nobr>XMM</nobr></code> register. The sourceoperand can be either an <code><nobr>XMM</nobr></code> register or a128-bit memory location.<h4><a name="section-B.4.10">B.4.10 <code><nobr>ANDNPS</nobr></code>: Bitwise Logical AND NOT of Packed Single-Precision FP Values</a></h4><p><pre>ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]