</pre><p><code><nobr>ANDNPS</nobr></code> inverts the bits of the foursingle-precision floating-point values in the destination register, andthen performs a logical AND between the four single-precisionfloating-point values in the source operand and the temporary invertedresult, storing the result in the destination register.<p><pre>   dst[0-31]   := src[0-31]   AND NOT dst[0-31],    dst[32-63]  := src[32-63]  AND NOT dst[32-63],    dst[64-95]  := src[64-95]  AND NOT dst[64-95],    dst[96-127] := src[96-127] AND NOT dst[96-127].</pre><p>The destination is an <code><nobr>XMM</nobr></code> register. The sourceoperand can be either an <code><nobr>XMM</nobr></code> register or a128-bit memory location.<h4><a name="section-B.4.11">B.4.11 <code><nobr>ANDPD</nobr></code>: Bitwise Logical AND For Single FP</a></h4><p><pre>ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]</pre><p><code><nobr>ANDPD</nobr></code> performs a bitwise logical AND of thetwo double-precision floating point values in the source and destinationoperand, and stores the result in the destination register.<p><pre>   dst[0-63]   := src[0-63]   AND dst[0-63],    dst[64-127] := src[64-127] AND dst[64-127].</pre><p>The destination is an <code><nobr>XMM</nobr></code> register. The sourceoperand can be either an <code><nobr>XMM</nobr></code> register or a128-bit memory location.<h4><a name="section-B.4.12">B.4.12 <code><nobr>ANDPS</nobr></code>: Bitwise Logical AND For Single FP</a></h4><p><pre>ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]</pre><p><code><nobr>ANDPS</nobr></code> performs a bitwise logical AND of thefour single-precision floating point values in the source and destinationoperand, and stores the result in the destination register.<p><pre>   dst[0-31]   := src[0-31]   AND dst[0-31],    dst[32-63]  := src[32-63]  AND dst[32-63],    dst[64-95]  := src[64-95]  AND dst[64-95],    dst[96-127] := src[96-127] AND dst[96-127].</pre><p>The destination is an <code><nobr>XMM</nobr></code> register. The sourceoperand can be either an <code><nobr>XMM</nobr></code> register or a128-bit memory location.<h4><a name="section-B.4.13">B.4.13 <code><nobr>ARPL</nobr></code>: Adjust RPL Field of Selector</a></h4><p><pre>ARPL r/m16,reg16              ; 63 /r                [286,PRIV]</pre><p><code><nobr>ARPL</nobr></code> expects its two word operands to besegment selectors. It adjusts the <code><nobr>RPL</nobr></code> (requestedprivilege level - stored in the bottom two bits of the selector) field ofthe destination (first) operand to ensure that it is no less (i.e. no moreprivileged than) the <code><nobr>RPL</nobr></code> field of the sourceoperand. The zero flag is set if and only if a change had to be made.<h4><a name="section-B.4.14">B.4.14 <code><nobr>BOUND</nobr></code>: Check Array Index against Bounds</a></h4><p><pre>BOUND reg16,mem               ; o16 62 /r            [186] BOUND reg32,mem               ; o32 62 /r            [386]</pre><p><code><nobr>BOUND</nobr></code> expects its second operand to point toan area of memory containing two signed values of the same size as itsfirst operand (i.e. two words for the 16-bit form; two doublewords for the32-bit form). It performs two signed comparisons: if the value in theregister passed as its first operand is less than the first of thein-memory values, or is greater than or equal to the second, it throws a<code><nobr>BR</nobr></code> exception. Otherwise, it does nothing.<h4><a name="section-B.4.15">B.4.15 <code><nobr>BSF</nobr></code>, <code><nobr>BSR</nobr></code>: Bit Scan</a></h4><p><pre>BSF reg16,r/m16               ; o16 0F BC /r         [386] BSF reg32,r/m32               ; o32 0F BC /r         [386]</pre><p><pre>BSR reg16,r/m16               ; o16 0F BD /r         [386] BSR reg32,r/m32               ; o32 0F BD /r         [386]</pre><ul><li><code><nobr>BSF</nobr></code> searches for the least significant setbit in its source (second) operand, and if it finds one, stores the indexin its destination (first) operand. If no set bit is found, the contents ofthe destination operand are undefined. If the source operand is zero, thezero flag is set.<li><code><nobr>BSR</nobr></code> performs the same function, but searchesfrom the top instead, so it finds the most significant set bit.</ul><p>Bit indices are from 0 (least significant) to 15 or 31 (mostsignificant). The destination operand can only be a register. The sourceoperand can be a register or a memory location.<h4><a name="section-B.4.16">B.4.16 <code><nobr>BSWAP</nobr></code>: Byte Swap</a></h4><p><pre>BSWAP reg32                   ; o32 0F C8+r          [486]</pre><p><code><nobr>BSWAP</nobr></code> swaps the order of the four bytes of a32-bit register: bits 0-7 exchange places with bits 24-31, and bits 8-15swap with bits 16-23. There is no explicit 16-bit equivalent: to byte-swap<code><nobr>AX</nobr></code>, <code><nobr>BX</nobr></code>,<code><nobr>CX</nobr></code> or <code><nobr>DX</nobr></code>,<code><nobr>XCHG</nobr></code> can be used. When<code><nobr>BSWAP</nobr></code> is used with a 16-bit register, the resultis undefined.<h4><a name="section-B.4.17">B.4.17 <code><nobr>BT</nobr></code>, <code><nobr>BTC</nobr></code>, <code><nobr>BTR</nobr></code>, <code><nobr>BTS</nobr></code>: Bit Test</a></h4><p><pre>BT r/m16,reg16                ; o16 0F A3 /r         [386] BT r/m32,reg32                ; o32 0F A3 /r         [386] BT r/m16,imm8                 ; o16 0F BA /4 ib      [386] BT r/m32,imm8                 ; o32 0F BA /4 ib      [386]</pre><p><pre>BTC r/m16,reg16               ; o16 0F BB /r         [386] BTC r/m32,reg32               ; o32 0F BB /r         [386] BTC r/m16,imm8                ; o16 0F BA /7 ib      [386] BTC r/m32,imm8                ; o32 0F BA /7 ib      [386]</pre><p><pre>BTR r/m16,reg16               ; o16 0F B3 /r         [386] BTR r/m32,reg32               ; o32 0F B3 /r         [386] BTR r/m16,imm8                ; o16 0F BA /6 ib      [386] BTR r/m32,imm8                ; o32 0F BA /6 ib      [386]</pre><p><pre>BTS r/m16,reg16               ; o16 0F AB /r         [386] BTS r/m32,reg32               ; o32 0F AB /r         [386] BTS r/m16,imm                 ; o16 0F BA /5 ib      [386] BTS r/m32,imm                 ; o32 0F BA /5 ib      [386]</pre><p>These instructions all test one bit of their first operand, whose indexis given by the second operand, and store the value of that bit into thecarry flag. Bit indices are from 0 (least significant) to 15 or 31 (mostsignificant).<p>In addition to storing the original value of the bit into the carryflag, <code><nobr>BTR</nobr></code> also resets (clears) the bit in theoperand itself. <code><nobr>BTS</nobr></code> sets the bit, and<code><nobr>BTC</nobr></code> complements the bit.<code><nobr>BT</nobr></code> does not modify its operands.<p>The destination can be a register or a memory location. The source canbe a register or an immediate value.<p>If the destination operand is a register, the bit offset should be inthe range 0-15 (for 16-bit operands) or 0-31 (for 32-bit operands). Animmediate value outside these ranges will be taken modulo 16/32 by theprocessor.<p>If the destination operand is a memory location, then an immediate bitoffset follows the same rules as for a register. If the bit offset is in aregister, then it can be anything within the signed range of the registerused (ie, for a 32-bit operand, it can be (-2^31) to (2^31 - 1)<h4><a name="section-B.4.18">B.4.18 <code><nobr>CALL</nobr></code>: Call Subroutine</a></h4><p><pre>CALL imm                      ; E8 rw/rd             [8086] CALL imm:imm16                ; o16 9A iw iw         [8086] CALL imm:imm32                ; o32 9A id iw         [386] CALL FAR mem16                ; o16 FF /3            [8086] CALL FAR mem32                ; o32 FF /3            [386] CALL r/m16                    ; o16 FF /2            [8086] CALL r/m32                    ; o32 FF /2            [386]</pre><p><code><nobr>CALL</nobr></code> calls a subroutine, by means of pushingthe current instruction pointer (<code><nobr>IP</nobr></code>) andoptionally <code><nobr>CS</nobr></code> as well on the stack, and thenjumping to a given address.<p><code><nobr>CS</nobr></code> is pushed as well as<code><nobr>IP</nobr></code> if and only if the call is a far call, i.e. adestination segment address is specified in the instruction. The formsinvolving two colon-separated arguments are far calls; so are the<code><nobr>CALL FAR mem</nobr></code> forms.<p>The immediate near call takes one of two forms(<code><nobr>call imm16/imm32</nobr></code>, determined by the currentsegment size limit. For 16-bit operands, you would use<code><nobr>CALL 0x1234</nobr></code>, and for 32-bit operands you woulduse <code><nobr>CALL 0x12345678</nobr></code>. The value passed as anoperand is a relative offset.<p>You can choose between the two immediate far call forms(<code><nobr>CALL imm:imm</nobr></code>) by the use of the<code><nobr>WORD</nobr></code> and <code><nobr>DWORD</nobr></code>keywords: <code><nobr>CALL WORD 0x1234:0x5678</nobr></code>) or<code><nobr>CALL DWORD 0x1234:0x56789abc</nobr></code>.<p>The <code><nobr>CALL FAR mem</nobr></code> forms execute a far call byloading the destination address out of memory. The address loaded consistsof 16 or 32 bits of offset (depending on the operand size), and 16 bits ofsegment. The operand size may be overridden using<code><nobr>CALL WORD FAR mem</nobr></code> or<code><nobr>CALL DWORD FAR mem</nobr></code>.<p>The <code><nobr>CALL r/m</nobr></code> forms execute a near call (withinthe same segment), loading the destination address out of memory or out ofa register. The keyword <code><nobr>NEAR</nobr></code> may be specified,for clarity, in these forms, but is not necessary. Again, operand size canbe overridden using <code><nobr>CALL WORD mem</nobr></code> or<code><nobr>CALL DWORD mem</nobr></code>.<p>As a convenience, NASM does not require you to call a far proceduresymbol by coding the cumbersome<code><nobr>CALL SEG routine:routine</nobr></code>, but instead allows theeasier synonym <code><nobr>CALL FAR routine</nobr></code>.<p>The <code><nobr>CALL r/m</nobr></code> forms given above are near calls;NASM will accept the <code><nobr>NEAR</nobr></code> keyword (e.g.<code><nobr>CALL NEAR [address]</nobr></code>), even though it is notstrictly necessary.<h4><a name="section-B.4.19">B.4.19 <code><nobr>CBW</nobr></code>, <code><nobr>CWD</nobr></code>, <code><nobr>CDQ</nobr></code>, <code><nobr>CWDE</nobr></code>: Sign Extensions</a></h4><p><pre>CBW                           ; o16 98               [8086] CWDE                          ; o32 98               [386]</pre><p><pre>CWD                           ; o16 99               [8086] CDQ                           ; o32 99               [386]</pre><p>All these instructions sign-extend a short value into a longer one, byreplicating the top bit of the original value to fill the extended one.<p><code><nobr>CBW</nobr></code> extends <code><nobr>AL</nobr></code> into<code><nobr>AX</nobr></code> by repeating the top bit of<code><nobr>AL</nobr></code> in every bit of <code><nobr>AH</nobr></code>.<code><nobr>CWDE</nobr></code> extends <code><nobr>AX</nobr></code> into<code><nobr>EAX</nobr></code>. <code><nobr>CWD</nobr></code> extends<code><nobr>AX</nobr></code> into <code><nobr>DX:AX</nobr></code> byrepeating the top bit of <code><nobr>AX</nobr></code> throughout<code><nobr>DX</nobr></code>, and <code><nobr>CDQ</nobr></code> extends<code><nobr>EAX</nobr></code> into <code><nobr>EDX:EAX</nobr></code>.<h4><a name="section-B.4.20">B.4.20 <code><nobr>CLC</nobr></code>, <code><nobr>CLD</nobr></code>, <code><nobr>CLI</nobr></code>, <code><nobr>CLTS</nobr></code>: Clear Flags</a></h4><p><pre>CLC                           ; F8                   [8086] CLD                           ; FC                   [8086] CLI                           ; FA                   [8086] CLTS                          ; 0F 06                [286,PRIV]</pre><p>These instructions clear various flags. <code><nobr>CLC</nobr></code>clears the carry flag; <code><nobr>CLD</nobr></code> clears the directionflag; <code><nobr>CLI</nobr></code> clears the interrupt flag (thusdisabling interrupts); and <code><nobr>CLTS</nobr></code> clears thetask-switched (<code><nobr>TS</nobr></code>) flag in<code><nobr>CR0</nobr></code>.<p>To set the carry, direction, or interrupt flags, use the<code><nobr>STC</nobr></code>, <code><nobr>STD</nobr></code> and<code><nobr>STI</nobr></code> instructions(<a href="#section-B.4.301">section B.4.301</a>). To invert the carry flag,use <code><nobr>CMC</nobr></code> (<a href="#section-B.4.22">sectionB.4.22</a>).<h4><a name="section-B.4.21">B.4.21 <code><nobr>CLFLUSH</nobr></code>: Flush Cache Line</a></h4><p><pre>CLFLUSH mem                   ; 0F AE /7        [WILLAMETTE,SSE2]</pre><p><code><nobr>CLFLUSH</nobr></code> invalidates the cache line thatcontains the linear address specified by the source operand from all levelsof the processor cache hierarchy (data and instruction). If, at any levelof the cache hierarchy, the line is inconsistent with memory (dirty) it iswritten to memory before invalidation. The source operand points to abyte-sized memory location.<p>Although <code><nobr>CLFLUSH</nobr></code> is flagged