?? regmap.h
字號:
#ifndef __REGMAP_DVD_H
#define __REGMAP_DVD_H
/*
** FILE
** regmap.h
**
** DESCRIPTION
** define register-file structure.
**
** NOTE:
** This is the DVD version.
*/
#include "types.h"
#include "dmabuf.h"
/*
** TYPE
** RegisterFile
*/
typedef struct
{
/*
** Group 0: Chip Information
** 0-3
*/
UINT32 stamp; /* 0: */
UINT32 emulation; /* 1: */
UINT32 reset; /* 2: */
UINT32 task_priority_set; /* 3: */
/*
** Group 1: timers
** 11-regs (4-15)
*/
UINT32 stc_15_0; /* 4 */
UINT32 stc_31_16; /* 5 */
UINT32 stc_32; /* 6 stc 33b counter @90kHz */
UINT32 stc_divisor; /* 7 */
UINT32 rtc_15_0; /* 8 */
UINT32 rtc_31_16; /* 9 */
UINT32 rtc_divisor; /* 10 */
UINT32 timer0_ctrl; /* 11 */
UINT32 timer0_cnt; /* 12 */
UINT32 timer1_ctrl; /* 13 */
UINT32 timer1_cnt; /* 14 */
/*
** Group 2 : Interrupt
**
** 15-16
*/
UINT32 intr_mask; /* 15: */
UINT32 intr_status; /* 16: */
/*
** Group 3 : Decoding control
**
** 17
*/
UINT32 pic_start; /* 17: */
/*
** Group 4 : Video bitstream parameters
**
** 13 regs
** 18-30:
*/
UINT32 seq_ext; /* 18 */
UINT32 h_size; /* 19 */
UINT32 v_size; /* 20 */
UINT32 qmx_par; /* 21 */
UINT32 pic_coding_type; /* 22 */
UINT32 pic_f_code; /* 23 */
UINT32 pic_coding_ext0; /* 24 */
UINT32 pic_coding_ext1; /* 25 */
UINT32 vld_ctrl; /* 26 */
UINT32 vld_status; /* 27 */
UINT32 bs_yinit; /* 28 */
UINT32 bs_xinit; /* 29 */
UINT32 video_decode_time; /* 30 */
/*
** Group 5 : SDRAM control
** 13 regs
** 31-34
*/
UINT32 evbya; /* 31 */
UINT32 eabya; /* 32 */
UINT32 ref0_luma; /* 33 */
UINT32 ref0_chroma; /* 34 */
UINT32 ref1_luma; /* 35 */
UINT32 ref1_chroma; /* 36 */
UINT32 bidir_luma; /* 37 */
UINT32 bidir_chroma; /* 38 */
UINT32 osdya; /* 39 */
UINT32 cdya; /* 40 */
UINT32 supya; /* 41 */
UINT32 audya; /* 42 */
UINT32 iopya; /* 43 */
UINT32 echoya; /* 44 */
/*
** Group 6: Display Control
*/
UINT32 dis_pic_id; /* 45 */
UINT32 dis_tv_std; /* 46 */
UINT32 dis_tv_out; /* 47 */
UINT32 dis_mixer; /* 48 */
UINT32 display_status; /* 49 */
/*
** Group 7 : RISC/SDRAM direct memory access
*/
UINT32 dma_mode; /* 50: */
UINT32 dma_yaddr; /* 51: */
UINT32 dma_xaddr; /* 52: */
UINT32 dma_done; /* 53: */
UINT32 lbc_control; //dma_addrlen;/* 54: SRAM addr/len */
UINT32 linesize; //dma_mode; /* 55: */
/*
** Group 8 : OSD control
** 3-regs
*/
UINT32 osd_en; /* 56: 1:enable OSD */
UINT32 tlink_addr; /* 57: */
UINT32 blink_addr; /* 58: */
/*
** Group 9: DSA
*/
UINT32 dsa_tx_reg; /* 59 */
UINT32 dsa_rx_reg; /* 60 */
UINT32 dsa_status; /* 61 */
/*
** Group 10: CDDSP
*/
UINT32 cddsp_vx; /* 62 */
UINT32 cddsp_vy; /* 63 */
UINT32 cddsp_config; /* 64 */
UINT32 cddsp_control; /* 65 */
UINT32 cddsp_mm_bcd; /* 66 */
UINT32 cddsp_ss_bcd; /* 67 */
UINT32 cddsp_ff_bcd; /* 68 */
UINT32 cddsp_status; /* 69 */
UINT32 cddsp_mmss; /* 70 */
UINT32 cddsp_ffmm; /* 71 */
/*
** Group 11: UART0/1
*/
UINT32 uart0_data; /* 72 : RBR_THR */
UINT32 uart0_lsr; /* 73 : LSR */
UINT32 uart0_msr; /* 74 : MSR */
UINT32 uart0_lcr; /* 75 : LCR */
UINT32 uart0_mcr; /* 76 : MCR */
UINT32 uart0_div_l; /* 77 : DIV_L_AD */
UINT32 uart0_div_h; /* 78 : DIV_H_AD */
UINT32 uart0_isc; /* 79 : ISC_AD */
UINT32 uart1_data; /* 80 : RBR_THR */
UINT32 uart1_lsr; /* 81 : LSR */
UINT32 uart1_msr; /* 82 : MSR */
UINT32 uart1_lcr; /* 83 : LCR */
UINT32 uart1_mcr; /* 84 : MCR */
UINT32 uart1_div_l; /* 85 : DIV_L_AD */
UINT32 uart1_div_h; /* 86 : DIV_H_AD */
UINT32 uart1_isc; /* 87 : ISC_AD */
/*
** Group 12 :I/O processor communication
*/
/* iop_data[0], iop_data[1], iop_data[2] is DSA status, Tx, Rx */
/* iop_data[0].0 tx full RISC set 1 when send, iop_data[0].1 rx full RISC clear 0 when receive */
/* iop_data[7] is for IR */
UINT32 iop_data[8]; /* 88 - 95 */
UINT32 iop_control; /* 96 */
UINT32 iop_status; /* 97 */
UINT32 iop_breakpoint; /* 98 */
UINT32 iop_reg_sel; /* 99 */
UINT32 iop_reg_out; /* 100 */
UINT32 iop_memlimit; /* 101 */
/*
** Group 13: VPP Control
*/
UINT32 dis_x_start; /* 102 */
UINT32 dis_y_start; /* 103 */
UINT32 dis_x_size; /* 104 */
UINT32 dis_y_size; /* 105 */
UINT32 v_filter_mode; /* 106: enable h/v filter */
// UINT32 field_exchange; /* 107 */
UINT32 h_exp_mode; /* 107 */
UINT32 dis_offset; /* 108 */
UINT32 offset_unused; /* 109 */
UINT32 luma_offset; /* 110 */
UINT32 chroma_offset; /* 111 */
UINT32 field_exchange; /* 112 */
UINT32 chroma_field_rep; /* 113 */
/*
** Group 14: SUP
*/
UINT32 sup_mode; /* 114 */
UINT32 sup_cmd_addr; /* 115 */
/*
** Group 15: EPP
*/
UINT32 epp_status; /* 116 */
UINT32 epp_data; /* 117 */
/*
** Group 16 : AUDIO CLOCK SELECTION
*/
UINT32 old_audio_clkgen; /* 118 */
/*
** Group 17 : Memory Configuration
*/
UINT32 video_compress; /* 119 */
UINT32 agdc_config; /* 120 */
UINT32 sdram_config; /* 121 */
UINT32 edo_config; /* 122 */
UINT32 watchdog; /* 123 */
UINT32 rom_config; /* 124 */
UINT32 rom1_base; /* 125 */
UINT32 rom2_base; /* 126 */
/*
** GROUP 18 : GPIO
*/
UINT32 gpio_sel; /* 127 */
UINT32 gpio_sel_aux; /* 128 */
UINT32 gpio_master[4]; /* 129-132 */
UINT32 gpio_oe[4]; /* 133-136 */
UINT32 gpio_out[4]; /* 137-140 */
UINT32 gpio_in[4]; /* 141-144 */
/*
** GROUP 19: monitor
*/
UINT32 mmu_mon[2]; // 145-146
UINT32 sys_mon[2]; // 147-148
UINT32 vld_mon[4]; // 149-152
UINT32 ogt_mon[4]; // 153-156
UINT32 agdc_mon_lbound; // 157
UINT32 agdc_mon_ubound; // 158
UINT32 agdc_mon_ctrl; // 159
/*
** GROUP 20: other
*/
UINT32 y_clip; //160
UINT32 cb_clip; //161
UINT32 mbuf_fill0; //162
UINT32 mbuf_fill1; //163
UINT32 game_mode; //164
UINT32 jpeg_control; //165
UINT32 jpeg_write_address; //166
UINT32 jpeg_write_data; //167
UINT32 jpeg_read_address; //168
UINT32 jpeg_read_data; //169
UINT32 intr_masked_status; //170
UINT32 invq_mode; //171
UINT32 bs_yrp; //172
UINT32 bs_ystop; //173
UINT32 clk0_en; //174
UINT32 clk1_en; //175
UINT32 gclk0_en; //176
UINT32 gclk1_en; //177
UINT32 audio_clkgen; //178
UINT32 video_clkgen; //179
UINT32 reg1_unused[12]; //180-191
UINT32 pos_pix; //192
UINT32 pos_line; //193
UINT32 pos_cfg; //194
UINT32 reg2_unused[5]; // 195-199
/*
** GROUP 21: priority
*/
UINT32 ds_priority; // 200
UINT32 mr_priority; // 201
UINT32 mw_priority; // 202
UINT32 ogt_priority; // 203
UINT32 osd_priority; // 204
UINT32 vr_priority; // 205
UINT32 rd_priority; // 206
UINT32 rl_priority; // 207
UINT32 x6502_priority; // 208
UINT32 pcm_priority; // 209
UINT32 aud_priority; // 210
UINT32 cd_priority; // 211
/*
** GROUP 22: I2C
UINT32 i2c_addr; // 212
UINT32 i2c_cmd; // 213
UINT32 i2c_data; // 214
UINT32 i2c_cfg; // 215
UINT32 i2c_func; // 216
UINT32 i2c_idx; // 217
/*
** GROUP 23: ROM protection
*/
UINT32 a0_tog; // 218
UINT32 a1_tog; // 219
UINT32 a2_tog; // 220
UINT32 d0_tog; // 221
UINT32 d1_tog; // 222
UINT32 d2_tog; // 223
UINT32 d_ror; // 224
UINT32 a0_mask; // 225
UINT32 a1_mask; // 226
UINT32 a2_mask; // 227
/*
** GROUP 24: TDM
*/
UINT32 tdm_config; // 228
UINT32 tdm_master; // 229
UINT32 tdm_status; // 230
UINT32 tdm_dout0; // 231
UINT32 tdm_dout1; // 232
UINT32 tdm_dout2; // 233
UINT32 tdm_dout3; // 234
UINT32 tdm_din0; // 235
UINT32 tdm_din1; // 236
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