?? stm32_init.c
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// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o27.2..3> TIM2_CCMR2.IC3PSC: Input Capture 3 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o27.0..1> TIM2_CCMR2.CC3S: Capture/compare 3 selection
// <i> Default: CC3 configured as output
// <0=> CC3 configured as output
// <1=> CC3 configured as input, IC3 mapped on TI3
// <2=> CC3 configured as input, IC3 mapped on TI4
// <3=> CC3 configured as input, IC3 mapped on TRGI
// <o28.9> TIM2_CCER.CC3P: Capture/compare 3 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o28.8> TIM2_CCER.CC3E: Capture/compare 3 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o31> TIM2_CCR3: Capture/compare register 3 <0-65535>
// <i> Set the Compare register value for compare register 3.
// <i> Default: 0
// </h>
//
//--------------------------------------------------------------------------- Timer 2 channel 4
// <h> Channel 4 Configuration
// <h> Channel configured as output
// <o27.15> TIM2_CCMR2.OC4CE: Output Compare 4 Clear enabled
// <o27.12..14> TIM2_CCMR2.OC4M: Output Compare 4 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 4 to active level on match
// <2=> Set channel 4 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o27.11> TIM2_CCMR2.OC4PE: Output Compare 4 Preload enabled
// <o27.10> TIM2_CCMR2.OC4FE: Output Compare 4 Fast enabled
// <o27.8..9> TIM2_CCMR2.CC4S: Capture/compare 4 selection
// <i> Default: CC4 configured as output
// <0=> CC4 configured as output
// <o28.13> TIM2_CCER.CC4P: Capture/compare 4 output Polarity set
// <i> Default: OC4 active high
// <0=> OC4 active high
// <1=> OC4 active low
// <o28.12> TIM2_CCER.CC4E: Capture/compare 4 output enabled
// <i> Default: OC4 not active
// <0=> OC4 not active
// <1=> OC4 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o27.12..15> TIM2_CCMR2.IC4F: Input Capture 4 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o27.10..11> TIM2_CCMR2.IC4PSC: Input Capture 4 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o27.8..9> TIM2_CCMR2.CC4S: Capture/compare 4 selection
// <i> Default: CC4 configured as output
// <0=> CC4 configured as output
// <1=> CC4 configured as input, IC4 mapped on TI4
// <2=> CC4 configured as input, IC4 mapped on TI3
// <3=> CC4 configured as input, IC4 mapped on TRGI
// <o28.13> TIM2_CCER.CC4P: Capture/compare 4 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o28.12> TIM2_CCER.CC4E: Capture/compare 4 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o32> TIM2_CCR4: Capture/compare register 4 <0-65535>
// <i> Set the Compare register value for compare register 4.
// <i> Default: 0
// </h>
//
// </e>
// <e3.1> TIM2 interrupts
// <o33.14> TIM2_DIER.TDE: Trigger DMA request enabled
// <o33.12> TIM2_DIER.CC4DE: Capture/Compare 4 DMA request enabled
// <o33.11> TIM2_DIER.CC3DE: Capture/Compare 3 DMA request enabled
// <o33.10> TIM2_DIER.CC2DE: Capture/Compare 2 DMA request enabled
// <o33.9> TIM2_DIER.CC1DE: Capture/Compare 1 DMA request enabled
// <o33.8> TIM2_DIER.UDE: Update DMA request enabled
// <o33.6> TIM2_DIER.TIE: Trigger interrupt enabled
// <o33.4> TIM2_DIER.CC4IE: Capture/Compare 4 interrupt enabled
// <o33.3> TIM2_DIER.CC3IE: Capture/Compare 3 interrupt enabled
// <o33.2> TIM2_DIER.CC2IE: Capture/Compare 2 interrupt enabled
// <o33.1> TIM2_DIER.CC1IE: Capture/Compare 1 interrupt enabled
// <o33.0> TIM2_DIER.UIE: Update interrupt enabled
// </e>
// </e>
//--------------------------------------------------------------------------- Timer 3 enabled
// <e1.2> TIM3 : Timer 3 enabled
// <o34> TIM3 period [us] <1-72000000:10>
// <i> Set the timer period for Timer 3.
// <i> Default: 1000 (1ms)
//--------------------------------------------------------------------------- Timer 3 detailed settings
// <e2.2> TIM3 detailed settings
// <o35> TIM3.PSC: Timer 3 Prescaler <0-65535>
// <i> Set the prescaler for Timer 3.
// <o36> TIM3.ARR: Timer 3 Auto-reload <0-65535>
// <i> Set the Auto-reload for Timer 3.
// <h> Timer 3 Control Register 1 Configuration (TIM3_CR1)
// <o37.8..9> TIM3_CR1.CKD: Clock division
// <i> Default: tDTS = tCK_INT
// <i> devision ratio between timer clock and dead time
// <0=> tDTS = tCK_INT
// <1=> tDTS = 2*tCK_INT
// <2=> tDTS = 4*tCK_INT
// <o37.7> TIM3_CR1.ARPE: Auto-reload preload enable
// <i> Default: Auto-reload preload disenabled
// <o37.5..6> TIM3_CR1.CMS: Center aligned mode selection
// <i> Default: Edge-aligned
// <0=> Edge-aligned
// <1=> Center-aligned mode1
// <2=> Center-aligned mode2
// <3=> Center-aligned mode3
// <o37.4> TIM3_CR1.DIR: Direction
// <i> Default: DIR = Counter used as up-counter
// <i> read only if timer is configured as Center-aligned or Encoder mode
// <0=> Counter used as up-counter
// <1=> Counter used as down-counter
// <o37.3> TIM3_CR1.OPM: One pulse mode enable
// <i> Default: One pulse mode disabled
// <o37.2> TIM3_CR1.URS: Update request source
// <i> Default: URS = Counter over-/underflow, UG bit, Slave mode controller
// <0=> Counter over-/underflow, UG bit, Slave mode controller
// <1=> Counter over-/underflow
// <o37.1> TIM3_CR1.UDIS: Update disable
// <i> Default: Update enabled
// </h>
//
// <h> Timer 3 Control Register 2 Configuration (TIM3_CR2)
// <o38.7> TIM3_CR2.TI1S: TI1 Selection
// <i> Default: TIM3CH1 connected to TI1 input
// <0=> TIM3CH1 connected to TI1 input
// <1=> TIM3CH1,CH2,CH3 connected to TI1 input
// <o38.4..6> TIM3_CR2.MMS: Master Mode Selection
// <i> Default: Reset
// <i> Select information to be sent in master mode to slave timers for synchronisation
// <0=> Reset
// <1=> Enable
// <2=> Update
// <3=> Compare Pulse
// <4=> Compare OC1REF iused as TRGO
// <5=> Compare OC2REF iused as TRGO
// <6=> Compare OC3REF iused as TRGO
// <7=> Compare OC4REF iused as TRGO
// <o38.3> TIM3_CR2.CCDS: Capture/Compare DMA Selection
// <i> Default: CC4 DMA request on CC4 event
// <0=> CC4 DMA request on CC4 event
// <1=> CC4 DMA request on update event
// </h>
//
// <h> Timer 3 Slave mode control register Configuration (TIM3_SMC)
// <o39.15> TIM3_SMCR.ETP: External trigger polarity
// <i> Default: ETR is non-inverted
// <0=> ETR is non-inverted
// <1=> ETR is inverted
// <o39.14> TIM3_SMCR.ECE: External clock mode 2 enabled
// <o39.12..13> TIM3_SMCR.ETPS: External trigger prescaler
// <i> Default: Prescaler OFF
// <0=> Prescaler OFF
// <1=> fETPR/2
// <2=> fETPR/4
// <3=> fETPR/8
// <o39.8..11> TIM3_SMCR.ETF: External trigger filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o39.7> TIM3_SMCR.MSM: Delay trigger input
// <o39.4..6> TIM3_SMCR.TS: Trigger Selection
// <i> Default: TIM1 (ITR0)
// <0=> TIM1 (ITR0)
// <1=> TIM2 (ITR1)
// <2=> TIM3 (ITR2)
// <3=> TIM4 (ITR3)
// <4=> TI1 Edge Detector (TI1F_ED)
// <5=> Filtered Timer Input 1 (TI1FP1)
// <6=> Filtered Timer Input 2 (TI1FP2)
// <7=> External Trigger Input (ETRF)
// <o39.0..2> TIM3_SMCR.SMS: Slave mode selection
// <i> Default: Slave mode disabled
// <0=> Slave mode disabled
// <1=> Encoder mode 1
// <2=> Encoder mode 2
// <3=> Encoder mode 3
// <4=> Reset mode
// <5=> Gated mode
// <6=> Trigger mode
// <7=> External clock mode 1
// </h>
//
//--------------------------------------------------------------------------- Timer 3 channel 1
// <h> Channel 1 Configuration
// <h> Channel configured as output
// <o40.7> TIM3_CCMR1.OC1CE: Output Compare 1 Clear enabled
// <o40.4..6> TIM3_CCMR1.OC1M: Output Compare 1 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 1 to active level on match
// <2=> Set channel 1 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o40.3> TIM3_CCMR1.OC1PE: Output Compare 1 Preload enabled
// <o40.2> TIM3_CCMR1.OC1FE: O?? 快捷鍵說明
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