?? main.c
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#define F0297_EXTADCLK_EN 128
#define F0297_ITLOCKSEL 129
#define F0297_ITPWMSEL 130
#define F0297_LOCKSCE 131
#define F0297_TWB_ACT 132
#define F0297_SOURCESEL 133
#define F0297_PRGCLKDIV 134
#define F0297_AUXCLKSEL 135
#define F0297_ITLOCK_OD 136
#define F0297_ITPWM_OD 137
#define F0297_AGC12SEL 138
#define F0297_AGC12B_EN 139
#define F0297_SIGMA_INV_1 140
#define F0297_SIGMA_INV_2 141
#define F0297_AUTOQAMMODE_SEL 142
#define F0297_AUTOCONSTEL_TIMER 143
#define F0297_AUTOSTOP_CONSTEL 144
#define F0297_AUTOCONSTEL_ON 145
#define F0297_DI_UNLOCK 146
#define F0297_DI_FREEZE 147
#define F0297_MISMATCH 148
#define F0297_ACQ_MODE 149
#define F0297_TRKMODE 150
#define F0297_SYNLOST 151
#define F0297_BERT_ON 152
#define F0297_ERR_SOURCE 153
#define F0297_ERR_MODE 154
#define F0297_NBYTE 155
#define F0297_ERRCOUNT_LO 156
#define F0297_ERRCOUNT_HI 157
#define F0297_USEINT 158
#define F0297_DAVIC 159
#define F0297_M 160
#define F0297_DEPTH 161
#define F0297_REFRESH47 162
#define F0297_BE_BYPASS 163
#define F0297_CKOUTPAR 164
#define F0297_CT_NBST 165
#define F0297_S_NP 166
#define F0297_TEI_ENA 167
#define F0297_DS_ENA 168
#define F0297_SYNC_STRIP 169
#define F0297_CI_EN 170
#define F0297_CICLK_POL 171
#define F0297_CICLK_BASE 172
#define F0297_CI_DIVRANGE 173
#define F0297_BK_CT_LO 174
#define F0297_BK_CT_HI 175
#define F0297_CORR_CT_LO 176
#define F0297_CORR_CT_HI 177
#define F0297_UNCORR_CT_HI 178
#define F0297_UNCORR_CT_LO 179
#define F0297_DIS_UNLOCK 180
#define F0297_MODE 181
#define F0297_CT_CLEAR 182
#define F0297_CT_HOLD 183
#define F0297_RS_NOCORR 184
#define F0297_SYNCSTATE 185
#define F0297_EN_CORNER_DET 186
#define F0297_TEST_SEL 187
#if 1
typedef unsigned char U8;
typedef unsigned int U32;
typedef unsigned short U16;
typedef int BOOL;
BOOL true=1;
BOOL false=0;
#endif
/*
* Copyright 2005 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*
* Not for distribution.
*/
/*
* I2C implementation
*
*/
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_I2C_init( ) *
* *
* Enable and initalize the I2C module *
* *
* The I2C clk is set to run at 20 KHz *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_I2C_init1( )
{
I2C_ICMDR = 0; // Reset I2C
I2C_ICPSC = 13; // Config prescaler for 27MHz
I2C_ICCLKL = 5; // Config clk LOW for 50kHz
I2C_ICCLKH = 5; // Config clk HIGH for 50kHz
I2C_ICMDR |= ICMDR_IRS; // Release I2C from reset
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_I2C_close( ) *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_I2C_close1( )
{
I2C_ICMDR = 0; // Reset I2C
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_I2C_reset( ) *
* *
* *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_I2C_reset1( )
{
DAVINCIEVM_I2C_close1( );
DAVINCIEVM_I2C_init1( );
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_I2C_write( i2caddr, data, len ) *
* *
* I2C write in Master mode *
* *
* i2caddr <- I2C slave address *
* data <- I2C data ptr *
* len <- # of bytes to write *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_I2C_write1( Uint16 i2caddr, Uint8* data, Uint16 len )
{
Uint16 i;
Int32 timeout = 0x20000;
Int32 timecount = 0;
I2C_ICCNT = len; // Set len
I2C_ICSAR = i2caddr; // Set I2C slave address
I2C_ICMDR = ICMDR_STT // Config for master write
| ICMDR_TRX
| ICMDR_MST
| ICMDR_IRS
| ICMDR_FREE
;
DAVINCIEVM_wait( 10 ); // Short delay
for ( i = 0 ; i < len ; i++ )
{
I2C_ICDXR = data[i]; // Write
timecount = 0;
do
{
timecount++;
if ( timecount >= timeout )
{
DAVINCIEVM_I2C_reset1( );
return 1000;
}
} while ( ( I2C_ICSTR & ICSTR_ICXRDY ) == 0 );// Wait for Tx Ready
}
I2C_ICMDR |= ICMDR_STP; // Generate STOP
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_I2C_read( i2caddr, data, len ) *
* *
* I2C read in Master mode *
* *
* i2caddr <- I2C slave address *
* data <- I2C data ptr *
* len <- # of bytes to write *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_I2C_read1( Uint16 i2caddr, Uint8* data, Uint16 len )
{
Uint16 i;
Int32 timeout = 0x20000;
Int32 timecount = 0;
I2C_ICCNT = len; // Set len
I2C_ICSAR = i2caddr; // Set I2C slave address
I2C_ICMDR = ICMDR_STT // Config for master read
| ICMDR_MST
| ICMDR_IRS
| ICMDR_FREE
;
for ( i = 0 ; i < len ; i++ )
{
timecount = 0;
do
{
timecount++;
if ( timecount >= timeout )
{
DAVINCIEVM_I2C_reset1( );
return 1000;
}
} while ( ( I2C_ICSTR & ICSTR_ICRRDY ) == 0 );// Wait for Rx Ready
data[i] = I2C_ICDRR; // Read
}
I2C_ICMDR |= ICMDR_STP; // Generate STOP
return 0;
}
typedef enum STTUNER_TSOutputMode_e
{
STTUNER_TS_MODE_DEFAULT, /* TS output not changeable */
STTUNER_TS_MODE_SERIAL, /* TS output serial */
STTUNER_TS_MODE_PARALLEL, /* TS output parallel */
STTUNER_TS_MODE_DVBCI /* TS output DVB-CI */
}
STTUNER_TSOutputMode_t;
typedef struct
{
U8 Address; /* Address U32 */
U8 ResetValue; /* Default (reset) value U32 */
U8 Value; /* Current value U32 */
}
STTUNER_IOREG_Registerb_t;
typedef struct
{
U8 Reg; /* Register index int */
U8 Pos; /* Bit position U32 */
U8 Bits; /* Bit width U32 */
U8 Type; /* Signed or unsigned U32 */
U8 Mask; /* Mask compute with width and position U32 */
}
STTUNER_IOREG_Fieldb_t;
typedef struct
{
U8 Registers; /* number of registers, e.g. 65 for stv0299 U32 */
U8 Fields; /* number of register fields, e.g. 113 for stv0299 U32 */
STTUNER_IOREG_Registerb_t *RegMap; /* register map list */
STTUNER_IOREG_Fieldb_t *FieldMap; /* register field list */
}
STTUNER_IOREG_DeviceMapb_t;
typedef enum STTUNER_Modulation_e
{
STTUNER_MOD_NONE = 0x00, /* Modulation unknown */
STTUNER_MOD_ALL = 0x3FF, /* Logical OR of all MODs */
STTUNER_MOD_QPSK = 1,
STTUNER_MOD_8PSK = (1 << 1),
STTUNER_MOD_QAM = (1 << 2),
STTUNER_MOD_4QAM = (1 << 3),
STTUNER_MOD_16QAM = (1 << 4),
STTUNER_MOD_32QAM = (1 << 5),
STTUNER_MOD_64QAM = (1 << 6),
STTUNER_MOD_128QAM = (1 << 7),
STTUNER_MOD_256QAM = (1 << 8),
STTUNER_MOD_BPSK = (1 << 9)
}
STTUNER_Modulation_t;
typedef enum STTUNER_Spectrum_e
{
STTUNER_INVERSION_NONE = 0,
STTUNER_INVERSION = 1,
STTUNER_INVERSION_AUTO = 2
}
STTUNER_Spectrum_t;
typedef enum
{
E297_NOCARRIER=0,
E297_CARRIEROK,
E297_NOAGC,
E297_AGCOK,
E297_AGCMAX,
E297_NOEQUALIZER,
E297_EQUALIZEROK,
E297_NODATA,
E297_DATAOK,
E297_LOCKOK
}
D0297_SignalType_t;
typedef enum STTUNER_J83_e
{
STTUNER_J83_NONE = 0x00,
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