?? net_nic.h
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/*
*********************************************************************************************************
* uC/TCP-IP
* The Embedded TCP/IP Suite
*
* (c) Copyright 2003-2007; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/TCP-IP is provided in source form for FREE evaluation, for educational
* use or peaceful research. If you plan on using uC/TCP-IP in a commercial
* product you need to contact Micrium to properly license its use in your
* product. We provide ALL the source code for your convenience and to help
* you experience uC/TCP-IP. The fact that the source code is provided does
* NOT mean that you can use it without paying a licensing fee.
*
* Network Interface Card (NIC) port files provided, as is, for FREE and do
* NOT require any additional licensing or licensing fee.
*
* Knowledge of the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* NETWORK INTERFACE CARD
*
* Davicom DM9000A
*
* Filename : net_nic.h
* Version : V1.90
* Programmer(s) : EHS
* BAN
*********************************************************************************************************
* Note(s) : (1) Supports EMAC section of Atmel's DM9000A microcontroller as described in
*
* Atmel Corporation (ATMEL; http://www.atmel.com).
*
* (2) REQUIREs Ethernet Network Interface Layer located in the following network directory :
*
* \<Network Protocol Suite>\IF\Ether\
*
* where
* <Network Protocol Suite> directory path for network protocol suite.
*********************************************************************************************************
*/
#ifndef __NET_NIC_H__
#define __NET_NIC_H__
/*
*********************************************************************************************************
* EXTERNS
*********************************************************************************************************
*/
#ifdef NET_NIC_MODULE
#define NET_NIC_EXT
#else
#define NET_NIC_EXT extern
#endif
/*
*********************************************************************************************************
* INCLUDE FILES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* DEFINES
*********************************************************************************************************
*/
#define DM9000A_10MHD 0
#define DM9000A_100MHD 1
#define DM9000A_10MFD 4
#define DM9000A_100MFD 5
#define DM9000A_AUTO 8
#define DM9000A_1M_HPNA 16
#define DM9000A_IO_8_BITS 1
#define DM9000A_IO_16_BITS 2
#define DM9000A_QUEUE_ONE_PACKET 1
#define DM9000A_QUEUE_TWO_PACKETS 2
#define DM9000A_ID 0x90000A46L
#define DM9000A_PKT_MAX 1536 /* Received packet max size */
#define DM9000A_PKT_RDY 0x01 /* Packet ready to receive */
/*
*********************************************************************************************************
* DM9000A REGISTER ADDRESS DEFINES
*********************************************************************************************************
*/
#define DM9000A_NCR 0x00 /* Network Control Register **/
#define DM9000A_NSR 0x01 /* Network Status Register **/
#define DM9000A_TCR 0x02 /* TX Control Register **/
#define DM9000A_TSR1 0x03 /* TX Status Register 1 **/
#define DM9000A_TSR2 0x04 /* TX Status Register 2 **/
#define DM9000A_RCR 0x05 /* RX Control Register **/
#define DM9000A_RSR 0x06 /* RX Status Register **/
#define DM9000A_ROCR 0x07 /* Receive Overflow Counter Register */
#define DM9000A_BPTR 0x08 /* Back Pressure Threshold Register */
#define DM9000A_FCTR 0x09 /* Flow Control Threshold Resgister */
#define DM9000A_FCR 0x0A /* RX Flow Control Register */
#define DM9000A_EPCR 0x0B /* EEPROM & PHY Control Register **/
#define DM9000A_EPAR 0x0C /* EEPROM & PHY Address Register */
#define DM9000A_EPDRL 0x0D /* EEPROM & PHY Low Byte Data Register */
#define DM9000A_EPDRH 0x0E /* EEPROM & PHY High Byte Data Register */
#define DM9000A_WCR 0x0F /* Wake Up Control Register (8-bit) */
#define DM9000A_PAR0 0x10 /* Physical Address Register, Byte 0 */
#define DM9000A_PAR1 0x11 /* " " " , Byte 1 */
#define DM9000A_PAR2 0x12 /* " " " , Byte 1 */
#define DM9000A_PAR3 0x13 /* " " " , Byte 1 */
#define DM9000A_PAR4 0x14 /* " " " , Byte 1 */
#define DM9000A_PAR5 0x15 /* " " " , Byte 1 */
#define DM9000A_MAR0 0x16 /* Multicast Address Register, Byte 0 */
#define DM9000A_MAR1 0x17 /* " " " , Byte 1 */
#define DM9000A_MAR2 0x18 /* " " " , Byte 2 */
#define DM9000A_MAR3 0x19 /* " " " , Byte 3 */
#define DM9000A_MAR4 0x1A /* " " " , Byte 4 */
#define DM9000A_MAR5 0x1B /* " " " , Byte 5 */
#define DM9000A_MAR6 0x1C /* " " " , Byte 6 */
#define DM9000A_MAR7 0x1D /* " " " , Byte 7 */
#define DM9000A_GPCR 0x1E /* General Purpose Control Register (8-bit) */
#define DM9000A_GPR 0x1F /* General Purpose Register */
#define DM9000A_TRPAL 0x22 /* TX SRAM Read Pointer Address Low Byte */
#define DM9000A_TRPAH 0x23 /* TX SRAM Read Pointer Address High Byte */
#define DM9000A_RWPAL 0x24 /* RX SRAM Write Pointer Address Low Byte */
#define DM9000A_RWPAH 0x25 /* RX SRAM Write Pointer Address High Byte */
#define DM9000A_VIDL 0x28 /* Vendor ID Low Byte */
#define DM9000A_VIDH 0x29 /* Vendor ID High Byte */
#define DM9000A_PIDL 0x2A /* Product ID Low Byte */
#define DM9000A_PIDH 0x2B /* Product ID High Byte */
#define DM9000A_CHIPR 0x2C /* Chip Revision */
#define DM9000A_TCR2 0x2D /* TX Control Register 2 */
#define DM9000A_OCR 0x2E /* Operation Control Register */
#define DM9000A_SMCR 0x2F /* Special Mode Control Register */
#define DM9000A_ETXCSR 0x30 /* Early Transmit Control/Status Register */
#define DM9000A_TCSCR 0x31 /* Transmit Check Sum Control Register */
#define DM9000A_RCSCSR 0x32 /* Receive Check Sum Control Status Register */
#define DM9000A_MPAR 0x33 /* MII PHY Address Register */
#define DM9000A_LEDCR 0x34 /* LED Pin Control Register */
#define DM9000A_BUSCR 0x38 /* Processor Bus Control Register */
#define DM9000A_INTCR 0x39 /* INT Pin Control Register */
#define DM9000A_PHY 0x40
#define DM9000A_SCCR 0x50 /* System Clock Turn ON Control Register */
#define DM9000A_RSCCR 0x51 /* Resume System Clock Control Register */
#define DM9000A_MRCMDX 0xF0 /* Memory Data Pre-Fetch Rd Cmd w/o Address Increment Reg. */
#define DM9000A_MRCMDX1 0xF1 /* Memory Data Read Command with Address Increment Reg. */
#define DM9000A_MRCMD 0xF2 /* Memory Data Read Command with Address Increment Reg. */
#define DM9000A_MRRH 0xF4 /* Memory Data Read Address Register Low Byte */
#define DM9000A_MRRL 0xF5 /* Memory Data Read Address Register High Byte */
#define DM9000A_MWCMDX 0xF6 /* Memory Data Write Command w/o Address Increment Reg. */
#define DM9000A_MWCMD 0xF8 /* Memory Data Write Command with Address Increment Reg. */
#define DM9000A_MWRL 0xFA /* Memory Data Write Address Register Low Byte */
#define DM9000A_MWRH 0xFB /* Memory Data Write Address Register High Byte */
#define DM9000A_TXPLL 0xFC /* TX Packet Length Low Byte Register */
#define DM9000A_TXPLH 0xFD /* TX Packet Length High Byte Register */
#define DM9000A_ISR 0xFE /* Interrupt Status Register **/
#define DM9000A_IMR 0xFF /* Interrupt Mask Register **/
/*
*********************************************************************************************************
* DM9000A PHY REGISTER ADDRESS DEFINES & REGISTER VALUE DEFINES
*********************************************************************************************************
*/
#define DM9000A_PHY_BMCR 0x00
#define DM9000A_PHY_BMSR 0x01
#define DM9000A_PHY_PHYID1 0x02
#define DM9000A_PHY_PHYID2 0x02
#define DM9000A_PHY_ANAR 0x04
#define DM9000A_PHY_ANLPAR 0x05
#define DM9000A_PHY_ANER 0x06
#define DM9000A_PHY_DSCR 0x10
#define DM9000A_PHY_DSCSR 0x11
#define DM9000A_PHY_10BTCSR 0x12
#define DM9000A_PHY_PWDOR 0x13
#define DM9000A_PHY_SPECCFG 0x17
/* Defines for PHY register [0x00] */
#define PHY_BMCR_RESET (1 << 15)
#define PHY_BMCR_LBK_EN (1 << 14)
#define PHY_BMCR_100MBPS (1 << 13)
#define PHY_BMCR_10MBPS (0 << 13)
#define PHY_BMCR_AN_EN (1 << 12)
#define PHY_BMCR_PWR_DN (1 << 11)
#define PHY_BMCR_ISOLATE (1 << 10)
#define PHY_BMCR_AN_RESTART (1 << 9)
#define PHY_BMCR_FDX (1 << 8)
#define PHY_BMCR_COLL_EN (1 << 7)
/* Defines for PHY register [0x01] */
#define PHY_BMSR_T4 (1 << 15)
#define PHY_BMSR_TX_FDX (1 << 14)
#define PHY_BMSR_TX_HDX (1 << 13)
#define PHY_BMSR_10_FDX (1 << 12)
#define PHY_BMSR_10_HDX (1 << 11)
#define PHY_BMSR_MF (1 << 6)
#define PHY_BMSR_AN_COMP (1 << 5)
#define PHY_BMSR_FAULT (1 << 4)
#define PHY_BMSR_AN_ABLE (1 << 3)
#define PHY_BMSR_LINK (1 << 2)
#define PHY_BMSR_JABBER (1 << 1)
#define PHY_BMSR_EXT (1 << 0)
/* Defines for PHY register [0x04] */
#define PHY_ANAR_NP (1 << 15)
#define PHY_ANAR_ACK (1 << 14)
#define PHY_ANAR_RF (1 << 13)
#define PHY_ANAR_FCS (1 << 10)
#define PHY_ANAR_T4 (1 << 9)
#define PHY_ANAR_TX_FDX (1 << 8)
#define PHY_ANAR_TX_HDX (1 << 7)
#define PHY_ANAR_10_FDX (1 << 6)
#define PHY_ANAR_10_HDX (1 << 5)
/*
*********************************************************************************************************
* DM9000A REGISTER VALUE DEFINES
*********************************************************************************************************
*/
/* Defines for register [0x00] */
#define NCR_WAKEEN (1 << 6)
#define NCR_FCOL (1 << 4)
#define NCR_FDX (1 << 3)
#define NCR_LBK_PHY (2 << 1)
#define NCR_LBK_MAC (1 << 1)
#define NCR_LBK_NORMAL (0 << 1)
#define NCR_RST (1 << 0)
/* Defines for register [0x01] */
#define NSR_SPEED (1 << 7)
#define NSR_LINKST (1 << 6)
#define NSR_WAKEST (1 << 5)
#define NSR_TX2END (1 << 3)
#define NSR_TX1END (1 << 2)
#define NSR_RXOV (1 << 1)
/* Defines for register [0x02] */
#define TCR_TJDIS (1 << 6)
#define TCR_EXCECM (1 << 5)
#define TCR_PAD_DIS2 (1 << 4)
#define TCR_CRC_DIS2 (1 << 3)
#define TCR_PAD_DIS1 (1 << 2)
#define TCR_CRC_DIS1 (1 << 1)
#define TCR_TXREQ (1 << 0)
/* Defines for register [0x03] */
/* Defines for register [0x04] */
#define TSR_TJTO (1 << 7)
#define TSR_LC (1 << 6)
#define TSR_NC (1 << 5)
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