//////////////////////////////////////////////////////////////////// Automatic Multiplier Generator Tool                      // This module generates VHDL code for mathematical expressions//// Writer      : Boris Kipnis// Last Update : 5/5/2005//#include "GenMathVHDL.h"#include <math.h>GenMathVHDL::GenMathVHDL(string fname) : GenVHDL(fname) {  tempCount = 0;}/////////////////////////////////////////////           ADD Variable                /////////////////////////////////////////////MathVHDL_var* GenMathVHDL::AddVariable(string nameIn, int type, int from=0, int to=0,			      int mathVarType=0,int shift=0,int sign=0,int termNum=0,                  int pipeStage=0,string str_label="",void* attach=NULL) {  MathVHDL_var* var;  int i;  string name;  name = nameIn;  for (i=0;i<pipeStage;i++) name+= "_d";  var = new MathVHDL_var(name,type,from,to,mathVarType,shift,sign,termNum,(-1),str_label,attach);  m_varList.push_back(var);  AddBaseVariable(var);  return(var);}MathVHDL_var* GenMathVHDL::AddVariable(MathVHDL_var* varIn,int pipeStage=0) {  string name;  int i;  MathVHDL_var* var;  name = varIn->GetVarName();  for (i=0;i<pipeStage;i++) name+= "_d";  var = new MathVHDL_var(name,varIn->GetVarType(),varIn->GetRangeFrom(),varIn->GetRangeTo(),			 varIn->GetMathVarType(),varIn->GetShift(),varIn->GetSign(),var->GetTermNum(),             varIn->GetPortType(),varIn->GetLabel(),varIn->GetAttachment());  m_varList.push_back(var);  AddBaseVariable(var);  return(var);}////////////////////////////////////////////////////////////                  Get Variable                        ////               from variables list                    ////////////////////////////////////////////////////////////MathVHDL_var* GenMathVHDL::GetVariable(string name) {  int i;  MathVHDL_var* var;    var = NULL;  for (i=0;i<m_varList.size();i++) {    if (name.compare(m_varList[i]->GetVarName()) == 0) { // scan variables      var = m_varList[i];    }    // if (name.compare(m_ioList[i]->GetVarName()) == 0) {  // scan IO ports    //     var = m_ioList[i];    // }  }  return(var);}MathVHDL_var* GenMathVHDL::GetVariable(string baseName,int pipeStage) {  for (int i=0;i<pipeStage;i++) baseName+="_d";  return(GetVariable(baseName));}vector<MathVHDL_var*> GenMathVHDL::GetVarList() {	return(m_varList);}void GenMathVHDL::SetVarList(vector<MathVHDL_var*> var) {	m_varList = var;}int GenMathVHDL::GetNextTemp() {  tempCount++;  return(tempCount-1);}int GenMathVHDL::GetCurTemp() {  return(tempCount);}string GenMathVHDL::GetNextTempName() {  int num;  char myChar[200];  num = GetNextTemp();  sprintf(myChar,"Temp%d",num);  return(myChar);}/////////////////////////////////////////////////////////////////////////////////////////  Generate Mathematics Variable From Multipliers Script                            /////////////////////////////////////////////////////////////////////////////////////////MathVHDL_var* GenMathVHDL::Script2MathVar(mult_s s,MathVHDL_var* DIn,vector<MathVHDL_var*> TermList) {  MathVHDL_var* var;  int sign;  int shift;  string name;  char myChar[200];  int termNum;  int type;  int i;    shift = s.shift;  termNum = s.termNum;  type = 0;  switch(s.type) {    case TERMT_PP :    case TERMT_PM :      var = new MathVHDL_var(TermList[termNum]);      break;     case TERMT_MM :    case TERMT_MP :      var = new MathVHDL_var(TermList[termNum]);      var->MultMinus1();      break;     case SIG_P    :      var = new MathVHDL_var(DIn);      break;     case SIG_M    :      var = new MathVHDL_var(DIn);      var->MultMinus1();      break;    default :      cout << "\r\nError at : GenMathVHDL::Script2MathVar\r\n";      var = NULL; // Generate System Error      break;  }   // update Shift  // Shift = (Original Variable Shift) + (Script Shift)  shift += var->GetShift();  var->SetShift(shift);    //printf("Script2MathVar Sign=%d Sign=%d\r\n",var->GetSign(),sign);  //cout << "Script2MathVar Label" << var->GetLabel() << "\r\n";  return(var);}// /////////////////////////////////////////////////////////// // Find variable by Name// MathVHDL_var* GenMathVHDL::FindVar(string name) {//   MathVHDL_var* var;////   var = NULL;//   for (int i=0;i<m_varList.size();i++) {//     if (!(name.compare(m_varList[i]->GetVarName()))) {//       var = m_varList[i];//     }//   }//   return(var);// }////////////////////////////////////////////////////////////////////////////////////////////////string GenMathVHDL::codeGen_ExtendBitSize(string varName,int addBits) {    int i;    ostringstream str_s;    str_s.clear();    //cout << "AddBits:" << addBits << "\r\n";	for (i=0;i<addBits;i++) {	   str_s << varName << "(" << varName << "'high) & ";	}	return(str_s.str());}string GenMathVHDL::codeGen_VarDownto(string varName,int downto) {    ostringstream str_s;	str_s << varName << "(" << varName << "'high downto " << downto << ")";	return(str_s.str());}string GenMathVHDL::codeGen_VarUp(string varName,int upTo) {    ostringstream str_s;	str_s << varName << "(" << upTo << " downto 0)";	return(str_s.str());}// Generate A +/- B VHDL codestring GenMathVHDL::codeGen_A_pm_B(MathVHDL_var* a,MathVHDL_var* b,MathVHDL_var* dest,int sign) {    ostringstream str_s;    int i;    	string aName,bName,destName;	int aShift,bShift,destShift;	int aSize,bSize,destSize;	int aTotalSize,bTotalSize,destTotalSize;	int aExtand,bExtand;	int delta,mDelta;	string sign_str;        aName      = a->GetVarName();    aShift     = a->GetShift();    aSize      = a->GetVarBitSize();    aTotalSize = aSize + aShift;	        bName      = b->GetVarName();    bShift     = b->GetShift();    bSize      = b->GetVarBitSize();	        bTotalSize = bSize + bShift;    destName      = dest->GetVarName();    destShift     = dest->GetShift();    destSize      = dest->GetVarBitSize();    destTotalSize = destSize + destShift;    aExtand = destTotalSize - aTotalSize; // calculate extansion from left    bExtand = destTotalSize - bTotalSize;    delta   = aShift-bShift;    mDelta  = bShift-aShift;    //cout << destName << " TotalSize=" << destTotalSize << " A_Extand:" << aExtand << " B_Extand:" << bExtand << " Delta:" << delta <<"\r\n";        if (delta<0) delta=0;    // don't use delta if bShift>aShift        // decrement common delta    //aExtand -= delta;    //bExtand -= delta;        // xbit + xbits = xbits + 1    //aExtand++;    //bExtand++;    if (sign>0) {       cout << "GenMathVHDL::codeGen_A_pm_B + \r\n";    	// + operation       str_s << "  -- " << destName << " = " << aName << "<<" << aShift << '+' << bName << "<<" << bShift << "\r\n";       str_s << "  " << destName << " <= (";       str_s << "(" << codeGen_ExtendBitSize(aName,aExtand) << aName << ") + \r\n"; // a(a'high) & a       str_s << "           ";       str_s << "(" << codeGen_ExtendBitSize(bName,bExtand) << codeGen_VarDownto(bName,delta);       if (mDelta>0) {       	  str_s << " & \"";       	  for (i=0;i<mDelta;i++) {       	  	str_s << "0";       	  }       	  str_s << "\"";       }       str_s << ")";       if (delta>0) str_s << " & " << codeGen_VarUp(bName,delta-1);       str_s << ");\r\n";       str_s << "\r\n";          } else {       cout << "GenMathVHDL::codeGen_A_pm_B - \r\n";       str_s << "  -- " << destName << " = " << aName << "<<" << aShift << '-' << bName << "<<" << bShift << "\r\n";       str_s << "  " << destName << " <= (";       str_s << "(" << codeGen_ExtendBitSize(aName,aExtand) << aName;       if (delta>0) {       	  str_s << " & \"";       	  for (i=0;i<delta;i++) {       	  	str_s << "0";       	  }       	  str_s << "\"";       }       str_s << ") - \r\n"; // a(a'high) & a       str_s << "           ";       str_s << "(" << codeGen_ExtendBitSize(bName,bExtand) << bName;       if (mDelta>0) {       	  str_s << " & \"";       	  for (i=0;i<mDelta;i++) {       	  	str_s << "0";       	  }       	  str_s << "\"";       }       str_s << ")";       str_s << ");\r\n";       str_s << "\r\n";    }        //cout << str_s.str();    return(str_s.str()); }string GenMathVHDL::codeGen_finalizeTerm(MathVHDL_var* a,MathVHDL_var* dest) {    int i;    string varName;    ostringstream str_s;        varName = dest->GetVarName();    varName = codeGen_ExtendBitSize(varName,dest->GetShift()-a->GetShift()) + varName;    if (a->GetShift()>0) {      varName += " & """;      for (i=0;i<a->GetShift();i++) {      	varName += "0";      }      varName += """";    }    varName += ";";     if (a->GetSign()>0) {       str_s << "-- Finalize: " << dest->GetVarName() << " = " << a->GetVarName() << "<<" << a->GetShift() << "\r\n";	       str_s << dest->GetVarName() << " <= " << varName;    } else {       str_s << "-- Finalize: " << dest->GetVarName() << " = (-1) * " << a->GetVarName() << "<<" << a->GetShift() << "\r\n";	       //str_s << dest->GetVarName() << " <= ";       str_s << dest->GetVarName() << " <= (not(" << varName << ")+1);" ;    }    return(str_s.str());}coreGen_element_s* GenMathVHDL::Gen_ZERO_Output() {   int destType;   string destName;   int termNum;   MathVHDL_var* destVar;	   coreGen_element_s *ret;	   destType = MatVHDL_var_TERM;   destName = GetNextTempName();   termNum  = GetCurTemp();          destVar = new MathVHDL_var(destName,VHDL_var_std_logic_vector,0,0,                    destType,0,1,termNum,                    0,"",NULL);   m_varList.push_back(destVar);   AddBaseVariable(destVar);   ret = new coreGen_element_s;      ret->a = destVar;    ret->b = destVar;    ret->dest = destVar;   ret->code = destVar->GetVarName() + " <= \"0\"; ";   ret->cmd = CMD_ZERO;   return(ret);}coreGen_element_s* GenMathVHDL::Gen_Lim_VHDL(MathVHDL_var* var,int NewBitSize) {	MathVHDL_var* destVar;	coreGen_element_s *ret;    ostringstream str_s;    int termNum;    int destType;    string destName;    string code;	//zzz	    destType = MatVHDL_var_TERM;    destName = GetNextTempName();    termNum  = GetCurTemp();        if (var->GetVarBitSize()<NewBitSize) {        NewBitSize = var->GetVarBitSize();    }            destVar = new MathVHDL_var(destName,VHDL_var_std_logic_vector,NewBitSize-1,0,                          destType,var->GetShift(),var->GetSign(),termNum,                          0,var->GetLabel(),var->GetAttachment());    m_varList.push_back(destVar);    AddBaseVariable(destVar);    str_s.clear();    str_s << "  " << destVar->GetVarName() << " <= " << var->GetVarName() << "(" << NewBitSize-1 << " downto 0); -- LIM \r\n";    code = str_s.str();// + "--- test --- \r\n";	ret = new coreGen_element_s;	ret->a = NULL;	ret->b = NULL;	ret->dest = destVar;	ret->cmd = CMD_LIM;	ret->code = code;    return(ret);}coreGen_element_s* GenMathVHDL::Gen_A_op_B_VHDL(int cmd,MathVHDL_var* aIn,MathVHDL_var* bIn=NULL,MathVHDL_var* DestIn=NULL) {	string code;	MathVHDL_var* destVar;	MathVHDL_var* tempVar;	coreGen_element_s *ret;		int aBitSize,bBitSize;	string aName,bName;	int aShift,bShift;	int aSize,bSize;	int aTotalSize,bTotalSize;	int aSign,bSign;	int destTotalSize,destShift,destSize,destSign;    int termNum;    int destType;    string destName;        int    tempInt;    string tempStr;	MathVHDL_var* a;	MathVHDL_var* b;	    int sign;	ret = new coreGen_element_s;		ret->cmd = cmd;	ret->a   = aIn;	ret->b   = bIn;