LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY coman IS 
  PORT( clk,aj,af,bj,bf,rd: IN STD_LOGIC;
        sh: out STD_LOGIC_VECTOR (7 DOWNTO 0);
        led7: out STD_LOGIC_VECTOR (6 DOWNTO 0));
END coman;

ARCHITECTURE behav OF coman IS
   COMPONENT selec
      PORT( clk: IN STD_LOGIC;
            selo: out STD_LOGIC_VECTOR (1 DOWNTO 0));
   end component;

   COMPONENT coma
      PORT( clk,aj,af,bj,bf,rd: IN STD_LOGIC;
            sh: out STD_LOGIC_VECTOR (7 DOWNTO 0);
            al,ah,bl,bh: out STD_LOGIC_VECTOR (3 DOWNTO 0));
    end component;

   COMPONENT ch1f4
      PORT( sele: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
            c0,c1,c2,c3: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            qout:out STD_LOGIC_VECTOR (3 DOWNTO 0));
    end component;

   COMPONENT decl7
      PORT( qin:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            led7s:out STD_LOGIC_VECTOR (6 DOWNTO 0));
    end component;
   SIGNAL b,c,d,e,f:STD_LOGIC_VECTOR (3 DOWNTO 0);
   SIGNAL a:STD_LOGIC_VECTOR (1 DOWNTO 0); 
  begin
   u1: selec PORT MAP(clk=>clk,selo=>a);    
   u2:  coma PORT MAP(clk,aj,af,bj,bf,rd,sh,b,c,d,e);
   u3: ch1f4 PORT MAP(a,b,c,d,e,f);
   u4: decl7 PORT MAP(f,led7);
END ARCHITECTURE behav;