#ifndef __TVDRX396XA_H__
#define __TVDRX396XA_H__


#define uint32_t unsigned long
#define uint16_t unsigned short
#define uint8_t  unsigned char
#define code Code
#define int8_t char
#define int16_t short
#define int32_t long

/******************************************************************************/
/**
 * DEFINES:
 ******************************************************************************/

/*  TV standards for DRX register STANDARD_SEL */
#define DRX_TVSTD_RESERVED_0   0x0000
#define DRX_TVSTD_RESERVED_1   0x0001
#define DRX_TVSTD_MN           0x0002
#define DRX_TVSTD_B            0x0103
#define DRX_TVSTD_G            0x0003
#define DRX_TVSTD_DK           0x0004
#define DRX_TVSTD_L            0x0009
#define DRX_TVSTD_LL           0x0109
#define DRX_TVSTD_I            0x000A
#define DRX_TVSTD_FM           0x0040

#define DRX_TVSTD_DEFAULT      DRX_TVSTD_B /** default value for TV standard */

/**  TV standards for DRX api-tv-standard functions */
enum DrxDrvTvStandard
{
/**  you need same order as in array awTvStd[DRX_TVSTD_MAX]!!! */

/** API index for awTvStd[] corresponding value of DRX register STANDARD_SEL */
   DRX_DRV_TVSTD_B,         /**  DRX_TVSTD_B */
   DRX_DRV_TVSTD_G,         /**  DRX_TVSTD_G */
   DRX_DRV_TVSTD_DK,        /**  DRX_TVSTD_DK */
   DRX_DRV_TVSTD_I,         /**  DRX_TVSTD_I */
   DRX_DRV_TVSTD_L,         /**  DRX_TVSTD_L */
   DRX_DRV_TVSTD_LL,        /**  DRX_TVSTD_LL */
   DRX_DRV_TVSTD_MN,        /**  DRX_TVSTD_MN */
   DRX_DRV_TVSTD_FM,        /**  DRX_TVSTD_FM */
   DRX_DRV_TVSTD_MAX        /**  account of api-tv-standard */
};

/**  IF frequencies for DRX register IF_FREQ */
#define DRX_IFFREQ_MN           0x0148
#define DRX_IFFREQ_B            0x013E
#define DRX_IFFREQ_G            0x0134
#define DRX_IFFREQ_DK           0x0134
#define DRX_IFFREQ_L            0x0134
#define DRX_IFFREQ_LL           0x0198
#define DRX_IFFREQ_I            0x0134
#define DRX_IFFREQ_FM           0x0040

#define DRX_IFFREQ_DEFAULT  DRX_IFFREQ_B  /** default value for IF frequency */


/**  IF frequencies for DRX api-if-frequency functions */
enum DrxApiIfFrequency
{
/**  you need same order as in array aIfFreq[DRX_IFFREQ_MAX]!!! */

/** API index for awIfFreq[]  corresponding value of DRX register IF_FREQ */
   DRX_DRV_IFFREQ_B,          /**  DRX_IFFREQ_B */
   DRX_DRV_IFFREQ_G,          /**  DRX_IFFREQ_G */
   DRX_DRV_IFFREQ_DK,         /**  DRX_IFFREQ_DK */
   DRX_DRV_IFFREQ_I,          /**  DRX_IFFREQ_I */
   DRX_DRV_IFFREQ_L,          /**  DRX_IFFREQ_L */
   DRX_DRV_IFFREQ_LL,         /**  DRX_IFFREQ_LL */
   DRX_DRV_IFFREQ_MN,         /**  DRX_IFFREQ_MN */
   DRX_DRV_IFFREQ_FM,         /**  DRX_IFFREQ_FM */
   DRX_DRV_IFFREQ_MAX         /**  account of api-if-frequency */
};



/******************************************************************************/
/**
 * GLOBAL FUNCTION PROTOTYPES:
 ******************************************************************************/

void DRX_DRV_SetTvStandard(uint16_t tvStd);
void DRX_DRV_SetCrAmpThDefaultValue(void);
void DRX_DRV_SetCrOvmThDefaultValue(void);
void DRX_DRV_SetVideoPeak(int8_t videoPeak);
void Drx_DRV_SetSifReferenceLevel(uint16_t sifRef);
void Drx_DRV_SetVideoReferenceLevel(uint16_t vidRef);
void Drx_DRV_SetTunerTakeOverPointSetting(uint16_t topSet);
void Drx_DRV_SetPhaseCorrectionBypass(uint16_t Val);

/*#if __IF_CONFIG__ == DRXA

void Drx_DRV_SetPort0(bool_t  Val);
void Drx_DRV_SetPort1(bool_t  Val);
void Drx_DRV_SetPort2(bool_t  Val);
void Drx_DRV_SetPort3(bool_t  Val);
void Drx_DRV_SetPort4(bool_t  Val);
void Drx_DRV_SetPort5(bool_t  Val);

#endif */

uint8_t  DRX_DRV_GetCrAmpThAtsValue(void);
uint8_t  DRX_DRV_GetCrOvmThAtsValue(void);
uint16_t Drx_DRV_GetStandardSelection(void);
uint16_t Drx_DRV_GetSifReferenceLevel(void);
uint16_t Drx_DRV_GetVideoReferenceLevel(void);
uint16_t Drx_DRV_GetTunerTakeOverPointSetting(void);
uint16_t Drx_DRV_GetVideoAgc(void);
uint16_t Drx_DRV_GetActualTunerGain(void);
uint16_t Drx_DRV_GetActualSifGain(void);
uint16_t Drx_DRV_GetAfcDeviation(void);
uint16_t Drx_DRV_GetAfcLockBit(void);
uint16_t Drx_DRV_GetAfcLockQuality(void);
#ifdef __RADIO_MODE__
uint16_t Drx_DRV_GetHardwareVersionCode(void);
uint16_t Drx_DRV_GetRomVersionCode(void);
#endif /* __RADIO_MODE__ */
uint16_t Drx_DRV_GetFamilyCode(void);
uint16_t Drx_DRV_GetMajorRevisionCode(void);
uint16_t Drx_DRV_GetProductCode(void);

/*#if __IF_CONFIG__ == DRXA
bool_t Drx_DRV_GetPort0(void);
bool_t Drx_DRV_GetPort1(void);
bool_t Drx_DRV_GetPort2(void);
bool_t Drx_DRV_GetPort3(void);
bool_t Drx_DRV_GetPort4(void);
bool_t Drx_DRV_GetPort5(void);
#endif */

int8_t   DRX_DRV_GetVideoPeak(void);

/*  help functions */
int8_t   DRX_DRV_GetTvStandardApiId(uint16_t tvStd);
uint16_t DRX_DrvGetTvStdDrxVal(uint8_t apiTvStd);

/******************************************************************************/
/*
 * GLOBAL FUNCTION PROTOTYPES:
 ******************************************************************************/

void Drx_InitBase(void);
void Drx_InitDrxA(void);
void Drx_InitDrxAts(void);
void Drx_NvmInit(void);


/******************************************************************************/
/*****************                                           ******************/
/*****************     BEGIN of Register Handler Section     ******************/
/*****************     =================================     ******************/
/*****************                                           ******************/
/******************************************************************************/

/*[#RH_SECTION_BEGIN]*/



/*====================================================================================================================*/
/*[#RHOH_REG - Drx]  Ver. 3.1.19 */

   /* Register Type ID's */

#define DRX_REGTYPE_I2C_XFP   0x01
#define DRX_REGTYPE_I2C16   0x02
#define DRX_REGTYPE_PORT   0x03


/* 'Number of' and 'Size' Constants */

#define DRX_NUM_REGISTERS       20
#define DRX_NUM_VARIABLES       2
#define DRX_NUM_BITSLICES       35
#define DRX_NUM_HIDDEN          0


/* 'Control' Constants */

#define DRX_CTRL_SIGNED          0x80
#define DRX_CTRL_READ            0x40
#define DRX_CTRL_WRITE           0x20
#define DRX_CTRL_SHIFT           0x1F

   /* Register Type */

 typedef struct _DRX_t
 {
    uint8_t  uCtrl;     /* DRX_CTRL_SIGNED, .._READ, .._WRITE, .._SHIFT */
    uint8_t  uType;     /* Register Type */
    uint16_t  uMask;     /* Mask within hardware register */
    uint16_t  uAddr;     /* Address */
    uint16_t  uVar;      /* Index of Shadow variable (0 = no variable) */
 } DRX_t;


   /* Bitslice Identifiers (index for drx[]) */

typedef enum
{
   DRX_NOTHING = 0,
   DRX_StandardSelection,
   DRX_FreqRespVideoPeakFilter,
   DRX_SifReferenceLevel,
   DRX_VideoReferenceLevel,
   DRX_FreqReferenceDividerSetting_8_0,
   DRX_TunerTakeOverPointSetting,
   DRX_CrOvmThBs,
   DRX_PhaseCorrectionBypass,
   DRX_CrAmpThBs,
   DRX_DirectIfFreqSetting,
   DRX_EqualizerUpdate,
   DRX_EqualizerCoefficientC0,
   DRX_EqualizerCoefficientC1,
   DRX_EqualizerCoefficientC2,
   DRX_EqualizerCoefficientC3,
   DRX_ActualVideoGain,
   DRX_ActualTunerGain,
   DRX_ActualSifGain,
   DRX_AfcLockBit,
   DRX_AfcDeviation,
   DRX_AfcLockQuality,
   DRX_HardwareVersionCode,
   DRX_FamilyCode,
   DRX_MajorRevisionCode,
   DRX_ProductCode,
   DRX_RomVersionCode,
   DRX_MspTimeOut,
   DRX_DrxTimeOut,
   DRX_DrxMspSoftwareReset,
   DRX_Port0,
   DRX_Port1,
   DRX_Port2,
   DRX_Port3,
   DRX_Port4,
   DRX_Port5
} DRX_ID_t;