; Total logic elements                        ; 77     ;
;     -- Combinational with no register       ; 68     ;
;     -- Register only                        ; 0      ;
;     -- Combinational with a register        ; 9      ;
;                                             ;        ;
; Logic element usage by number of LUT inputs ;        ;
;     -- 4 input functions                    ; 49     ;
;     -- 3 input functions                    ; 19     ;
;     -- 2 input functions                    ; 8      ;
;     -- 1 input functions                    ; 1      ;
;     -- 0 input functions                    ; 0      ;
;         -- Combinational cells for routing  ; 0      ;
;                                             ;        ;
; Logic elements by mode                      ;        ;
;     -- normal mode                          ; 77     ;
;     -- arithmetic mode                      ; 0      ;
;     -- qfbk mode                            ; 0      ;
;     -- register cascade mode                ; 0      ;
;     -- synchronous clear/load mode          ; 0      ;
;     -- asynchronous clear/load mode         ; 0      ;
;                                             ;        ;
; Total registers                             ; 9      ;
; I/O pins                                    ; 20     ;
; Maximum fan-out node                        ; dir[0] ;
; Maximum fan-out                             ; 22     ;
; Total fan-out                               ; 291    ;
; Average fan-out                             ; 3.00   ;
+---------------------------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                     ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |lift                      ; 77 (77)     ; 9            ; 0           ; 0            ; 0       ; 0         ; 0         ; 20   ; 0            ; 68 (68)      ; 0 (0)             ; 9 (9)            ; 0 (0)           ; 0 (0)      ; |lift               ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; ladd[1]                                       ;   ;
; ur[1]                                         ;   ;
; ur[2]                                         ;   ;
; ur[5]                                         ;   ;
; ur[6]                                         ;   ;
; ur[3]                                         ;   ;
; ur[4]                                         ;   ;
; ladd[0]                                       ;   ;
; Number of user-specified and inferred latches ; 8 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 9     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |lift|liftor[1]            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |lift|wai_t[1]             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/fpga例子/lift/lift.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Dec 17 22:19:38 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lift -c lift
Info: Found 2 design units, including 1 entities, in source file lift.vhd
    Info: Found design unit 1: lift-lift_arch
    Info: Found entity 1: lift
Info: Elaborating entity "lift" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at lift.vhd(27): object "delayx" assigned a value but never read
Warning (10631): VHDL Process Statement warning at lift.vhd(48): signal or variable "ur" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ur" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10631): VHDL Process Statement warning at lift.vhd(48): signal or variable "dr" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "dr" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10631): VHDL Process Statement warning at lift.vhd(65): signal or variable "ladd" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ladd" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10492): VHDL Process Statement warning at lift.vhd(104): signal "divide" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Duplicate registers merged to single register
    Info: Duplicate register "divide" merged to single register "dir[0]"
Warning: Latch ladd[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal rtl~0
Warning: Latch ur[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal p2~0
Warning: Latch ur[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal p2~0
Warning: Latch ur[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal p2~0
Warning: Latch ur[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal p2~0
Warning: Latch ur[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal p2~0
Warning: Latch ur[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal p2~0
Warning: Latch ladd[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal liftor[2]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "run_wait[3]" stuck at GND
Info: Implemented 97 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 13 output pins
    Info: Implemented 77 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings
    Info: Processing ended: Mon Dec 17 22:19:42 2007
    Info: Elapsed time: 00:00:05