?? sta.vhd
字號:
library IEEE;
use IEEE.std_logic_1164.all;
entity sta is
port (
clk:in std_logic;
dir:out std_logic_vector(2 downto 0);
divide:out std_logic
);
end sta;
architecture a of sta is
signal did:std_logic;
signal dirr:std_logic_vector(2 downto 0);
begin
process(clk)
begin
if (clk'event and clk='1') then
did<=not did;
if(dirr="100") then dirr<="000";
else dirr<=dirr+1;
end if;
end if;
end process;
divide<=did;dir<=dirr;
end a;
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