{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 19 16:43:22 2007 " "Info: Processing started: Wed Dec 19 16:43:22 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sta -c sta " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sta -c sta" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sta.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sta.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sta-a " "Info: Found design unit 1: sta-a" {  } { { "sta.vhd" "" { Text "D:/fpga例子/lift/sta/sta.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sta " "Info: Found entity 1: sta" {  } { { "sta.vhd" "" { Text "D:/fpga例子/lift/sta/sta.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_NO_UNIQUE_OPER_DEFN_MATCH" "0 \"+\" sta.vhd(19) " "Error (10327): VHDL error at sta.vhd(19): can't determine definition of operator \"\"+\"\" -- found 0 possible definitions" {  } { { "sta.vhd" "" { Text "D:/fpga例子/lift/sta/sta.vhd" 19 0 0 } }  } 0 10327 "VHDL error at %3!s!: can't determine definition of operator \"%2!s!\" -- found %1!d! possible definitions" 0 0}
{ "Error" "EVRFX_VHDL_UNIT_INGONRED_ERR" "a sta.vhd(10) " "Error (10523): Ignored construct a at sta.vhd(10) due to previous errors" {  } { { "sta.vhd" "" { Text "D:/fpga例子/lift/sta/sta.vhd" 10 0 0 } }  } 0 10523 "Ignored construct %1!s! at %2!s! due to previous errors" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Wed Dec 19 16:43:23 2007 " "Error: Processing ended: Wed Dec 19 16:43:23 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}