library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity reg is
	port (
		up:in STD_LOGIC;
		down:in STD_LOGIC;
		dir: in std_logic_vector(2 downto 0);
		st_ch:in STD_LOGIC;
		run_stop:in STD_LOGIC;
		lift:out std_logic_vector(2 downto 0);
		up,down:out std_logic_vector(6 downto 1)
		 );
end reg;
architecture a of reg is
signal liftor:std_logic_vector(2 downto 0);	--樓選指示及樓層數計數器
signal wai_t:std_logic_vector(2 downto 0);	--運行或等待計數器
signal hand:std_logic;						--時鐘2分頻和樓選復位變量
 begin
	lift<=liftor;
	process(dir,up,down,st_ch,liftor,wai_t,run_stop,hand)--該進程完成樓層請求寄存器的置位與復位
	variable num,t:integer;
	begin
		num:=conv_integer(liftor)+1;
		t:=conv_integer(dir)+1;
		if (run_stop='1') then
			if(((t>num) and (st_ch='1')) or (up='1')) then up(t)<='1';
			elsif (hand='1') then ur(num)<='0';
			end if;
			if(((t<num) and (st_ch='1')) or (down='1')) then down(t)<='1';
			elsif (hand='1') then dr(num)<='0';
			end if;
		else up<="000000";
			down<="000000";
		end if;
	end process;
end a;