?? cl_de.vhd
字號:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity cl_de is
port (
divide:in STD_LOGIC;
ladd:in std_logic_vector(1 downto 0);
wai_t: out std_logic_vector(2 downto 0);
lift:out std_logic_vector(2 downto 0);
);
end cl_de;
architecture a of cl_de is
signal waitfor,liftor:std_logic_vector(2 downto 0);
begin
wai_t<=waitfor;
lift<=liftor;
process(waitfor,ladd,closex,delayx)
begin
if (divide'event and divide='1') then
if waitfor="000" then waitfor<="101";
else
if (delay='0') then waitfor<=waitfor-1;
else waitfor<="010";
end if;
if (waitfor="001") then
if(ladd="11") then liftor<=liftor+1;
elsif(ladd="10") then liftor<=liftor-1;
end if;
end if;
end if;
end if;
end process;
end a;
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