?? uart_rxerr_tb.vhd

?? UART參考設計
?? VHD
?? 第 1 頁 / 共 3 頁
字號:
    DCDn <= '1';
    DSRn <= '1';
    RIn  <= '1';

    wait for (9.5*CLK_PERIOD);

    MR <= '0';

    wait for (0.5*CLK_PERIOD);


    wait until falling_edge(PCLK);
    -- Test 1 ----------------------------------------------------
    --   8-bit data, Overrun Error test
    TestID <= 1;
    
    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 1, enable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 0, disable received data available interrupt
    write_reg (IER,"00000100",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, even parity selected
    --   bit 3 : 0, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 8 data bit (bit[1-0]="11")
    --   bit 0 : 1, 8 data bit (bit[1-0]="11")
    write_reg (LCR,"00000011",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait until data received
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "Data Ready" flag at bit 0 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(0) = '1';
        i := i + 1;
      else
        assert (false) report"Data Receiving Failed"
        severity failure;
      end if;
    end loop;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is pending due to Overrun
    read_reg (IIR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00000110"
      report"Invalid IIR"
      severity failure;

    -- Read and check LSR (check if "Overrun Error" flag at bit 1 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100011"
      report"Invalid LSR"
      severity failure;

    -- Check if INTR is low
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Read and check LSR (check if "Overrun Error" flag at bit 1 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01010110"
      report"Invalid RBR"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01010110"
      report"Invalid RBR"
      severity failure;


    wait until falling_edge(PCLK);
    -- Test 2 ----------------------------------------------------
    --   8-bit data, Parity Error test, even parity
    TestID <= 2;
    
    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 1, enable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 0, disable received data available interrupt
    write_reg (IER,"00000100",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 1, even parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 8 data bit (bit[1-0]="11")
    --   bit 0 : 1, 8 data bit (bit[1-0]="11")
    write_reg (LCR,"00011011",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait until data received
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "Data Ready" flag at bit 0 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(0) = '1';
        i := i + 1;
      else
        assert (false) report"Data Receiving Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is low
    assert INTR = '0'
      report"Interrupt should not be generated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "10010010"
      report"Invalid RBR"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Read and check LSR (check if "Parity Error" flag at bit 2 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100101"
      report"Invalid LSR"
      severity failure;

    -- Check if INTR is low
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Read and check LSR (read again to see if it's changed by LSR read)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "10010010"
      report"Invalid RBR"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;


    wait until falling_edge(PCLK);
    -- Test 3 ----------------------------------------------------
    --   8-bit data, Parity Error test, odd parity
    TestID <= 3;
    
    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 1, enable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 0, disable received data available interrupt
    write_reg (IER,"00000100",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 8 data bit (bit[1-0]="11")
    --   bit 0 : 1, 8 data bit (bit[1-0]="11")
    write_reg (LCR,"00001011",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait until data received
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "Data Ready" flag at bit 0 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(0) = '1';
        i := i + 1;
      else
        assert (false) report"Data Receiving Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is low
    assert INTR = '0'
      report"Interrupt should not be generated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "10010010"
      report"Invalid RBR"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Read and check LSR (check if "Parity Error" flag at bit 2 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100101"
      report"Invalid LSR"
      severity failure;

    -- Check if INTR is low
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Read and check LSR (read again to see if it's changed by LSR read)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "10010010"
      report"Invalid RBR"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;


    wait until falling_edge(PCLK);
    -- Test 4 ----------------------------------------------------
    --   8-bit data, Parity Error test, stick even parity
    TestID <= 4;
    
    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 1, enable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 0, disable received data available interrupt
    write_reg (IER,"00000100",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 1, stick parity
    --   bit 4 : 1, even parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 8 data bit (bit[1-0]="11")
    --   bit 0 : 1, 8 data bit (bit[1-0]="11")
    write_reg (LCR,"00111011",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait until data received
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "Data Ready" flag at bit 0 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(0) = '1';
        i := i + 1;
      else
        assert (false) report"Data Receiving Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is low
    assert INTR = '0'
      report"Interrupt should not be generated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "10010010"
      report"Invalid RBR"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
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?? uart_rxerr_tb.vhd

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