?? uart_rxerr_tb.vhd
字號(hào):
report"Invalid LSR"
severity failure;
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Read and check LSR (check if "Parity Error" flag at bit 2 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100101"
report"Invalid LSR"
severity failure;
-- Check if INTR is low
assert INTR = '0'
report"Interrupt not negated"
severity failure;
-- Read and check LSR (read again to see if it's changed by LSR read)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100001"
report"Invalid LSR"
severity failure;
-- Read and check RBR
read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "10010010"
report"Invalid RBR"
severity failure;
-- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100000"
report"Invalid LSR"
severity failure;
wait until falling_edge(PCLK);
-- Test 5 ----------------------------------------------------
-- 8-bit data, Parity Error test, stick odd parity
TestID <= 5;
-- IER Intialization
-- bit 3 : 0, disable modem status interrupt
-- bit 2 : 1, enable receiver line status interrupt
-- bit 1 : 0, disable tranmitter holding register empty interrupt
-- bit 0 : 0, disable received data available interrupt
write_reg (IER,"00000100",CS,ADSn,WRn,A,DIN);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 1, stick parity
-- bit 4 : 0, odd parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 0, 1 stop bit
-- bit 1 : 1, 8 data bit (bit[1-0]="11")
-- bit 0 : 1, 8 data bit (bit[1-0]="11")
write_reg (LCR,"00101011",CS,ADSn,WRn,A,DIN);
-- trigger okToReceiveSIN to get character from SIN
okToReceiveSIN <= '1',
'0' after 1 ns;
-- Wait until data received
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "Data Ready" flag at bit 0 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(0) = '1';
i := i + 1;
else
assert (false) report"Data Receiving Failed"
severity failure;
end if;
end loop;
-- Check if INTR is low
assert INTR = '0'
report"Interrupt should not be generated"
severity failure;
-- Read and check RBR
read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "10010010"
report"Invalid RBR"
severity failure;
-- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100000"
report"Invalid LSR"
severity failure;
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Read and check LSR (check if "Parity Error" flag at bit 2 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100101"
report"Invalid LSR"
severity failure;
-- Check if INTR is low
assert INTR = '0'
report"Interrupt not negated"
severity failure;
-- Read and check LSR (read again to see if it's changed by LSR read)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100001"
report"Invalid LSR"
severity failure;
-- Read and check RBR
read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "10010010"
report"Invalid RBR"
severity failure;
-- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100000"
report"Invalid LSR"
severity failure;
wait until falling_edge(PCLK);
-- Test 6 ----------------------------------------------------
-- 8-bit data, Framing Error test, resync failed
TestID <= 6;
-- IER Intialization
-- bit 3 : 0, disable modem status interrupt
-- bit 2 : 1, enable receiver line status interrupt
-- bit 1 : 0, disable tranmitter holding register empty interrupt
-- bit 0 : 0, disable received data available interrupt
write_reg (IER,"00000100",CS,ADSn,WRn,A,DIN);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 1, stick parity
-- bit 4 : 0, odd parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 0, 1 stop bit
-- bit 1 : 1, 8 data bit (bit[1-0]="11")
-- bit 0 : 1, 8 data bit (bit[1-0]="11")
write_reg (LCR,"00101011",CS,ADSn,WRn,A,DIN);
-- trigger okToReceiveSIN to get character from SIN
okToReceiveSIN <= '1',
'0' after 1 ns;
-- Wait until data received
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "Data Ready" flag at bit 0 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(0) = '1';
i := i + 1;
else
assert (false) report"Data Receiving Failed"
severity failure;
end if;
end loop;
-- Check if INTR is low
assert INTR = '0'
report"Interrupt should not be generated"
severity failure;
-- Read and check RBR
read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01110100"
report"Invalid RBR"
severity failure;
-- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100000"
report"Invalid LSR"
severity failure;
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Read and check LSR (check if "Framing Error" flag at bit 3 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01101001"
report"Invalid LSR"
severity failure;
-- Check if INTR is low
assert INTR = '0'
report"Interrupt should be negated now"
severity failure;
-- Read and check LSR (read again to see if it's changed by LSR read)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100001"
report"Invalid LSR"
severity failure;
-- Read and check RBR
read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01110100"
report"Invalid RBR"
severity failure;
-- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100000"
report"Invalid LSR"
severity failure;
wait until falling_edge(PCLK);
-- Test 7 ----------------------------------------------------
-- 8-bit data, Break Interrupt test
TestID <= 8;
-- IER Intialization
-- bit 3 : 0, disable modem status interrupt
-- bit 2 : 1, enable receiver line status interrupt
-- bit 1 : 0, disable tranmitter holding register empty interrupt
-- bit 0 : 0, disable received data available interrupt
write_reg (IER,"00000100",CS,ADSn,WRn,A,DIN);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 0, not stick parity
-- bit 4 : 0, odd parity selected
-- bit 3 : 0, parity disabled
-- bit 2 : 0, 1 stop bit
-- bit 1 : 1, 8 data bit (bit[1-0]="11")
-- bit 0 : 1, 8 data bit (bit[1-0]="11")
write_reg (LCR,"00000011",CS,ADSn,WRn,A,DIN);
-- trigger okToReceiveSIN to get character from SIN
okToReceiveSIN <= '1',
'0' after 1 ns;
-- Wait until data received
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "Data Ready" flag at bit 0 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(0) = '1';
i := i + 1;
else
assert (false) report"Data Receiving Failed"
severity failure;
end if;
end loop;
-- Check if INTR is low
assert INTR = '0'
report"Interrupt should not be generated"
severity failure;
-- Read and check RBR
read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "11111111"
report"Invalid RBR"
severity failure;
-- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100000"
report"Invalid LSR"
severity failure;
-- Wait for INTR high
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
exit when INTR = '1';
i := i + 1;
else
assert (false) report"Interrupt Generation Failed"
severity failure;
end if;
end loop;
-- Read and check LSR (check if "Break Interrupt" flag at bit 4 is set)
-- ("Framing Error" should also be set in this case)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01111001"
report"Invalid LSR"
severity failure;
-- Check if INTR is low
assert INTR = '0'
report"Interrupt not negated"
severity failure;
-- Read and check LSR (read again to see if it's changed by LSR read)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100001"
report"Invalid LSR"
severity failure;
-- Read and check RBR
read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "00000000"
report"Invalid RBR"
severity failure;
-- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
assert regData_readBack = "01100000"
report"Invalid LSR"
severity failure;
-- end of tests ----------------------------------------------
assert (false)
report"End of UART Receiver Error Tests ....."
severity failure;
end process UART_Stim_Proc;
-- *** end of test bench ***
end;
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