/* sysLib.c - HITSAT OMU system-dependent routines *//* Copyright 2004 HITSAT Limited */#include "copyright_wrs.h"/*DESCRIPTIONThis library provides board-specific routines for the OMU Development Board BSP.It includes the following chip drivers:	nullVme.c...................dummy VMEbus routines	s3c2410xIntrCtl.c...........s3c2410x interrupt controller driver	s3c2410xTimer.c.............s3c2410x timer driver	s3c2410xSio.c...............s3c2410x UART driver include by sysSerial.cif INCLUDE_FLASH is defined, it includes:	flashMem.c..................Flash memory driver	nvRamToFlash.c..............driver to use some Flash like NVRAMelse it #includes:	nullNvRam.c.................dummy NVRAM routinesIt includes the following BSP files:	sysSerial.c.................serial device initialisation routines	sysEnd.c....................END network driver support routines.*//* includes */#include "vxWorks.h"#include "config.h"#include "sysLib.h"#include "string.h"#include "intLib.h"#include "taskLib.h"#include "vxLib.h"#include "muxLib.h"#include "cacheLib.h"#include "arch/arm/mmuArmLib.h"#include "private/vmLibP.h"#include "dllLib.h"/* imports */IMPORT char end[];			    /* end of system, created by ld */IMPORT VOIDFUNCPTR _func_armIntStackSplit;  /* ptr to fn to split stack */#if !defined(INCLUDE_MMU) && \    (defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU_BASIC) || \     defined(INCLUDE_MMU_FULL) || defined(INCLUDE_MMU_MPU))#define INCLUDE_MMU#endif/* globals */#if defined(INCLUDE_MMU)/* * The following structure describes the various different parts of the * memory map to be used only during initialisation by * vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC/FULL are * defined. * * Clearly, this structure is only needed if the CPU has an MMU! * * The following are not the smallest areas that could be allocated for a * working system. If the amount of memory used by the page tables is * critical, they could be reduced. */PHYS_MEM_DESC sysPhysMemDesc [] ={	/*	 * ROM is normally marked as uncacheable by VxWorks. We leave it like that	 * for the time being, even though this has a severe impact on execution	 * speed from ROM.	 */	{		(void *) (ROM_BASE_ADRS+0xf0000000),		(void *) (ROM_BASE_ADRS),		ROUND_UP (ROM_SIZE_TOTAL*2, PAGE_SIZE),		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE_NOT  | VM_STATE_CACHEABLE_NOT	},	{		(void *) (0x08000000),		(void *) (0x08000000),                  /* Flash2, 2MB */		ROUND_UP (0x00200000, PAGE_SIZE),		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE  | VM_STATE_CACHEABLE_NOT	},	{		(void *) (0x10000000),		(void *) (0x10000000),                  /* FPGA, 16MB */		ROUND_UP (0x01000000, PAGE_SIZE),		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE  | VM_STATE_CACHEABLE_NOT	},    	/* adrs and length parameters must be page-aligned (multiples of 0x1000) */    	/* RAM */	{		(void *) LOCAL_MEM_LOCAL_ADRS,	/* virtual address */		(void *) LOCAL_MEM_LOCAL_ADRS,	/* physical address */		ROUND_UP (LOCAL_MEM_SIZE, PAGE_SIZE), /* length, then initial state: */		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE	},	{		(void *) 0,	/* virtual address */		(void *) LOCAL_MEM_LOCAL_ADRS,	/* physical address */		ROUND_UP (LOCAL_MEM_SIZE, PAGE_SIZE), /* length, then initial state: */		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE	},	/*	 * I/O space:	 * Do not map in all I/O space, only that which has something there.	 * Otherwise we will use all of RAM allocating page tables!	 */	{		(void *) 0x28000000,		/* CS8900A  */		(void *) 0x28000000,		ROUND_UP (SZ_4M, PAGE_SIZE),		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT	},	{		(void *) 0x48000000,		/* Memory controller */		(void *) 0x48000000,		PAGE_SIZE,		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT	},	{		(void *) 0x4a000000,		/* Interrupt controller */		(void *) 0x4a000000,		PAGE_SIZE,		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT	},	{		(void *) 0x4c000000,		/* System & Clock controller */		(void *) 0x4c000000,		PAGE_SIZE,		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT	},	{		(void *) UART_0_BASE_ADR,	/* UART 0 */		(void *) UART_0_BASE_ADR,		PAGE_SIZE,		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT	},	{		(void *) UART_1_BASE_ADR,	/* UART 1 */		(void *) UART_1_BASE_ADR,		PAGE_SIZE,		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT	},	{		(void *) s3c2410x_TIMER_BASE,	/* Timer&Counter */		(void *) s3c2410x_TIMER_BASE,		PAGE_SIZE,		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT	},	{		(void *) 0x4e000000,             /* NAND-flash controller */		(void *) 0x4e000000,		PAGE_SIZE,		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT	},	{		(void *) 0x53000000,		/* WatchDog controller */		(void *) 0x53000000,		PAGE_SIZE,		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT	},	{		(void *) 0x56000000,		/* GPIO controller */		(void *) 0x56000000,		PAGE_SIZE,		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT	},	{		(void *) 0x59000000,		/* SPI controller */		(void *) 0x59000000,		PAGE_SIZE,		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT	}};int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);#endif /* defined(INCLUDE_MMU) */int	sysBus	    = BUS;		/* system bus type (VME_BUS, etc) */int	sysCpu	    = CPU;		/* system CPU type (e.g. ARMARCH4/4_T)*/char *	sysBootLine = BOOT_LINE_ADRS; 	/* address of boot line */char *	sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */int	sysProcNum;			/* processor number of this CPU */int	sysFlags;			/* boot flags */char	sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */char	sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted *//* locals *//* * List of interrupts to be serviced in order of decreasing priority. * Interrupts not in this list will be serviced least-significant bit * first at a lower priority than those in the list. * * To use lowest-bit = highest-priority, reverse the sense of the * condition below so that s3c2410xIntLvlPriMap is a zero pointer. *//* defines *//* externals *//*IMPORT int  s3c2410xIntDevInit (void);*/IMPORT void sysIntStackSplit (char*, long);/* globals *//* forward LOCAL functions declarations *//* forward declarations */char *	sysPhysMemTop (void);/* included source files */#include "mem/nullNvRam.c"#include "vme/nullVme.c"#include "s3c2410xIntrCtl.c"#include "s3c2410xTimer.c"#include "sysSerial.c"/* #include "cs8900a.c" */#ifdef INCLUDE_END#include "cs8900aEnd.c"#endif/* * sysModel - return the model name of the CPU board * * This routine returns the model name of the CPU board. * * NOTE * This routine does not include all of the possible variants, and the * inclusion of a variant in here does not mean that it is supported. * * RETURNS: A pointer to a string identifying the board and CPU. */char* sysModel(void){   	return "HITSAT OMU - S3C2410X(Samsung)";}/* * sysBspRev - return the BSP version with the revision eg 1.2/<x> * * This function returns a pointer to a BSP version with the revision. * e.g. 1.2/<x>. BSP_REV is concatenated to BSP_VERSION to form the * BSP identification string. * * RETURNS: A pointer to the BSP version/revision string. */char* sysBspRev(void){	return (BSP_VERSION BSP_REV);}/* * sysHwInit0 - perform early BSP-specific initialisation * * This routine performs such BSP-specific initialisation as is necessary before * the architecture-independent cacheLibInit can be called. It is called * from usrInit() before cacheLibInit(), before sysHwInit() and before BSS * has been cleared. * * RETURNS: N/A */void sysHwInit0(void){#ifdef INCLUDE_CACHE_SUPPORT	/*	 * Install the appropriate cache library, no address translation	 * routines are required for this BSP, as the default memory map has	 * virtual and physical addresses the same.	 */	cacheArm920tLibInstall (NULL, NULL);#endif	/* INCLUDE_CACHE_SUPPORT */#if defined(INCLUDE_MMU)	/* Install the appropriate MMU library and translation routines */	mmuArm920tLibInstall (NULL, NULL);#endif	/* defined(INCLUDE_MMU) */	return;}/* * sysHwInit - initialize the CPU board hardware * * This routine initializes various features of the hardware. * Normally, it is called from usrInit() in usrConfig.c. * * NOTE: This routine should not be called directly by the user. * * RETURNS: N/A */void sysHwInit(void){	/* install the IRQ/SVC interrupt stack splitting routine */	_func_armIntStackSplit = sysIntStackSplit;#ifdef INCLUDE_SERIAL	/* initialise the serial devices */	sysSerialHwInit ();      /* initialise serial data structure */#endif	/* INCLUDE_SERIAL */}/* * sysHwInit2 - additional system configuration and initialization * * This routine connects system interrupts and does any additional * configuration necessary.  Note that this is called from * sysClkConnect() in the timer driver. * * RETURNS: N/A * */void sysHwInit2(void){	static BOOL initialised = FALSE;	if(initialised) return;	/* initialise the interrupt library and interrupt driver */	intLibInit (s3c2410x_INT_NUM_LEVELS, s3c2410x_INT_NUM_LEVELS, INT_MODE);	s3c2410xIntDevInit();	/* connect sys clock interrupt and auxiliary clock interrupt */	(void)intConnect (INUM_TO_IVEC (SYS_TIMER_INT_VEC), sysClkInt, 0);	(void)intConnect (INUM_TO_IVEC (AUX_TIMER_INT_VEC), sysAuxClkInt, 0);#ifdef INCLUDE_SERIAL	/* connect serial interrupt */	sysSerialHwInit2();#endif	/* INCLUDE_SERIAL */	initialised = TRUE;}/* * sysPhysMemTop - get the address of the top of physical memory * * This routine returns the address of the first missing byte of memory, * which indicates the top of memory. * * Normally, the user specifies the amount of physical memory with the * macro LOCAL_MEM_SIZE in config.h.  BSPs that support run-time * memory sizing do so only if the macro LOCAL_MEM_AUTOSIZE is defined. * If not defined, then LOCAL_MEM_SIZE is assumed to be, and must be, the * true size of physical memory. * * NOTE: Do no adjust LOCAL_MEM_SIZE to reserve memory for application * use.  See sysMemTop() for more information on reserving memory. * * RETURNS: The address of the top of physical memory. * * SEE ALSO: sysMemTop() */char* sysPhysMemTop(void){	static char * physTop = NULL;	if(physTop == NULL)	{#ifdef LOCAL_MEM_AUTOSIZE	/* If auto-sizing is possible, this would be the spot.  */#	error   "Dynamic memory sizing not supported"#else	/* Don't do autosizing, if size is given */	physTop = (char *)(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE);#endif	/* LOCAL_MEM_AUTOSIZE */	}	return physTop;}/* * sysMemTop - get the address of the top of VxWorks memory * * This routine returns a pointer to the first byte of memory not * controlled or used by VxWorks. * * The user can reserve memory space by defining the macro USER_RESERVED_MEM * in config.h.  This routine returns the address of the reserved memory * area.  The value of USER_RESERVED_MEM is in bytes. * * RETURNS: The address of the top of VxWorks memory. */char* sysMemTop(void){	static char * memTop = NULL;	if(memTop == NULL)	{		memTop = sysPhysMemTop () - USER_RESERVED_MEM;	}	return memTop;}/* * sysToMonitor - transfer control to the ROM monitor * * This routine transfers control to the ROM monitor.  It is usually called * only by reboot() -- which services ^X -- and bus errors at interrupt * level.  However, in some circumstances, the user may wish to introduce a * new <startType> to enable special boot ROM facilities. * * RETURNS: Does not return. *//* startType, passed to ROM to tell it how to boot */STATUS sysToMonitor(int startType){	FUNCPTR	pRom;	UINT32* p = (UINT32 *)ROM_TEXT_ADRS;#ifdef INCLUDE_SERIAL	sysSerialReset ();	/* put serial devices into quiet state */#endif	/*	 * Examine ROM - if it's a VxWorks boot ROM, jump to the warm boot entry	 * point; otherwise jump to the start of the ROM.	 * A VxWorks boot ROM begins	 *    MOV	R0,#BOOT_COLD	 *    B	...	 *    DCB	"Copyright"	 * We check the first and third words only. This could be tightened up	 * if required (see romInit.s).	 */	if(p[0] == 0xE3A00002 && p[2] == 0x79706F43)		pRom = (FUNCPTR)(ROM_TEXT_ADRS + 0x24);	/* warm boot address */	else		pRom = (FUNCPTR)(ROM_TEXT_ADRS + 0x20);	/* start of ROM */	VM_ENABLE(FALSE);	/* disable the MMU, cache(s) and write-buffer */	/*	 * On 920T, can have the I-cache enabled once the MMU has been	 * disabled, so, unlike the other processors, disabling the MMU does	 * not disable the I-cache.  This would not be a problem, as the	 * 920T boot ROM initialisation code disables and flushes both caches.	 * However, in case we are, in fact, using a 7TDMI boot ROM,	 * disable and flush the I-cache here, or else the boot process may	 * fail.	 */	cacheDisable (INSTRUCTION_CACHE);	(*pRom)(startType);	/* jump to boot ROM */	return OK;		/* in case we ever continue from ROM monitor */}/* * sysProcNumGet - get the processor number * * This routine returns the processor number for the CPU board, which is * set with sysProcNumSet(). * * RETURNS: The processor number for the CPU board. * * SEE ALSO: sysProcNumSet() */int sysProcNumGet(void){	return sysProcNum;}/* * sysProcNumSet - set the processor number * * Set the processor number for the CPU board.  Processor numbers should be * unique on a single backplane. * * NOTE * By convention, only processor 0 should dual-port its memory. * * RETURNS: N/A * * SEE ALSO: sysProcNumGet() *//* procNum, processor number */void sysProcNumSet(int procNum){	sysProcNum = procNum;}