/* ads860.h - Motorola MPC860ADS board header *//* Copyright 1984-1997 Wind River Systems, Inc. *//*modification history--------------------01p,12jun02,kab  SPR 74987: cplusplus protection01o,29jan02,dtr  Removing netif driver info.01n,26oct01,dtr  Added define KEYED_REG_UNLOCK_VALUE related to  SPR65678.01m,03oct00,js  Added support for 850SARDB cpu.01l,06feb99,cn   added support for SDRAM (SPR# 24337), also changed		 N_SIO_CHANNELS to 2 (SPR# 10005).01i,06jan99,cn   added support for FADS860T boards.01h,18feb98,gls  added support for PPC823FADS01g,12nov97,map  added SYS_CPU_FREQ [SPR# 9366]01f,11nov97,hdn  added PC_xxx macros for TFFS.01e,10nov96,tpr  replaved SYS_CLK_FREQ by SPLL_FREQ_REQUESTED.01d,08nov96,tpr  added DEC_CLOCK_FREQ.01c,06nov96,tpr  added macros + clean up.01b,28may96,dzb  changed to 24Mhz clock speed.01a,19apr96,tpr  written.*//*This file contains I/O addresses and related constants for theMotorola MPC860ads board. */#ifndef	INCads860h#define	INCads860h#ifdef __cplusplus    extern "C" {#endif#include "drv/mem/memDev.h"#include "drv/intrCtl/ppc860Intr.h"#define BUS	0				/* bus-less board */#define CPU	PPC860				/* CPU type */#define N_SIO_CHANNELS	 	2		/* No. serial I/O channels */#define FREQ_20_MHZ		20000000	/* 20 Mhz */#define FREQ_25_MHZ		25000000	/* 25 Mhz */#define FREQ_50_MHZ		50000000	/* 50 Mhz */#define	PC_BASE_ADRS_0		0x02000000	/* PCMCIA base address */#define	PC_SIZE_0		0x00100000	/* PCMCIA mapping size */#define	PC_BASE_ADRS_1		0x04000000	/* PCMCIA base address */#define	PC_SIZE_1		0x02000000	/* PCMCIA mapping size *//* RTC register values *//* Key Register Unlock Value */#define KEYED_REG_UNLOCK_VALUE		0x55CCAA33/*  * SPLL Multiplication Factor: use to set the MF bits of the PLPRCR register. * PLPRCR is set by sysHwInit() in sysLib.c.  * SPLL_FREQ_REQUESTED and CRISTAL_FREQ are defined in config.h */#define SPLL_MUL_FACTOR	((SPLL_FREQ_REQUESTED / CRISTAL_FREQ) - 1)/*  * SPLL Multiplication Factor to get a 20 MHZ running frequency */#define SPLL_MUL_FACTOR_20MHZ	((FREQ_20_MHZ / CRISTAL_FREQ) - 1)/* * SPLL Frequency - gives the SPLL real frequency divide by 2 */#define SPLL_FREQ	((SPLL_MUL_FACTOR + 1) * CRISTAL_FREQ)/* * Baud Rate Generator Clock - gives the Baud Rate Generator Clock (BRGCLK) * Frequency.  */#define BRGCLK_FREQ	(SPLL_FREQ / ( 1 << (2 * BRGCLK_DIV_FACTOR)))/*  * Refresh value - defines the number of BRGCLK period between two  * DRAM refresh cycle. */#define REFRESH_VALUE	(BRGCLK_FREQ / DRAM_REFRESH_FREQ)/*  * Periodic Timer A period - value used to set the PTA bits of * the Machine A Mode Register (MAMR). This register is used to * controle the User_Programmable Machine A (UPM). The UPM is part of * the memory controller. */#define PTA_VALUE	(( REFRESH_VALUE / 64) != 0 ? (REFRESH_VALUE / 64) : \			 ((REFRESH_VALUE / 32) != 0 ? (REFRESH_VALUE / 32) : \			 ((REFRESH_VALUE / 16) != 0 ? (REFRESH_VALUE / 16) : \			 ((REFRESH_VALUE /  8) != 0 ? (REFRESH_VALUE /  8) : \			 ((REFRESH_VALUE /  4) != 0 ? (REFRESH_VALUE /  4) : \			  (REFRESH_VALUE /  2))))))/*  * Periodic Timer Prescaler Division Factor - gives the division factor * of the Periodic Timer Prescaler (PTP). The PTP is part of the  * memory controller. It divide the BRGCLK (Baud Rate Generator Clock) by * either 2, 4, 8, 16, 32 or 64 and send this divided clock to the * Periodic Timer.  * This macro is used to set the DRAM refresh cycle period. */#define PTP_DIV_FACTOR	(REFRESH_VALUE / PTA_VALUE)/* * PTP Value - translate the Periodic Timer Prescaler Division Factor  * to the value to place in the PTP register. */#define PTP_VALUE	( PTP_DIV_FACTOR ==  2 ? MPTPR_PTP_DIV2 : \			 (PTP_DIV_FACTOR ==  4 ? MPTPR_PTP_DIV4 : \			 (PTP_DIV_FACTOR ==  8 ? MPTPR_PTP_DIV8 : \			 (PTP_DIV_FACTOR == 16 ? MPTPR_PTP_DIV16 : \			 (PTP_DIV_FACTOR == 32 ? MPTPR_PTP_DIV32 : \			  MPTPR_PTP_DIV64)))))/* */#define TMBCLK_FREQ	CRISTAL_FREQ/* define the decrementer input clock frequency */#define DEC_CLOCK_FREQ	TMBCLK_FREQ/* define system clock rate */#define	SYS_CPU_FREQ	SPLL_FREQ/* Internal Memory Map base Address */#define INTERNAL_MEM_MAP_ADDR		0x02200000	#define INTERNAL_MEM_MAP_SIZE		0x00010000	/* 64 K bytes *//* size of the on-board SDRAM */#define SDRAM_SIZE			0x00400000	/* 4 Meg */#define SDRAM_REFRESH_FREQ		64000		/* 64 Khz *//* Board Status and Control Registers - unique to ADS */#define	BCSR_BASE_ADDR	0x02100000	/* BCSR base address *//* Port A pin map */#define	PA00	0x08000#define	PA01	0x04000#define	PA02	0x02000#define	PA03	0x01000#define	PA04	0x08800#define	PA05	0x00400#define	PA06	0x00200#define	PA07	0x00100#define	PA08	0x00080#define	PA09	0x00040#define	PA10	0x00020#define	PA11	0x00010#define	PA12	0x00008#define	PA13	0x00004#define	PA14	0x00002#define	PA15	0x00001/* Port B pin map */#define	PB14	0x20000#define	PB15	0x10000#define	PB16	0x08000#define	PB17	0x04000#define	PB18	0x02000#define	PB19	0x01000#define	PB20	0x00800#define	PB21	0x00400#define	PB22	0x00200#define	PB23	0x00100#define	PB24	0x00080#define	PB25	0x00040#define	PB26	0x00020#define	PB27	0x00010#define	PB28	0x00008#define	PB29	0x00004#define	PB30	0x00002#define	PB31	0x00001/* Port C pin map */#define	PC04	0x00800#define	PC05	0x00400#define	PC06	0x00200#define	PC07	0x00100#define	PC08	0x00080#define	PC09	0x00040#define	PC10	0x00020#define	PC11	0x00010#define	PC12	0x00008#define	PC13	0x00004#define	PC14	0x00002#define	PC15	0x00001#ifdef _ASMLANGUAGE#define BCSR0		BCSR_BASE_ADDR 		/* Register 0 */#define BCSR1		BCSR_BASE_ADDR + 0x04	/* Register 1 */#define BCSR2		BCSR_BASE_ADDR + 0x08	/* Register 2 */#define BCSR3		BCSR_BASE_ADDR + 0x0c	/* Register 3 */#define BCSR4		BCSR_BASE_ADDR + 0x10	/* Register 4 */#else#define BCSR0		((VINT32 *) (BCSR_BASE_ADDR))		/* Register 0 */#define BCSR1		((VINT32 *) (BCSR_BASE_ADDR + 0x04))	/* Register 1 */#define BCSR2		((VINT32 *) (BCSR_BASE_ADDR + 0x08))	/* Register 2 */#define BCSR3		((VINT32 *) (BCSR_BASE_ADDR + 0x0c))	/* Register 3 */#define BCSR4		((VINT32 *) (BCSR_BASE_ADDR + 0x10))	/* Register 4 */#endif	/* _ASMLANGUAGE *//* BCSR0 bit definition */#define BCSR0_ERB			0x80000000	/* BCSR0 */#define BCSR0_IP_L			0x40000000	/* 0 = ROM */#define BCSR0_BDIS			0x10000000	/* boot disable */#define BCSR0_PORT_SIZE_32		0x00000000	/* CS0~ port size */#define BCSR0_PORT_SIZE_16		0x08000000	/* CS0~ port size */#define BCSR0_PORT_SIZE_8		0x04000000	/* CS0~ port size */#define BCSR0_MEM_SPACE_0		0x00000000	/* initial mem space */#define BCSR0_MEM_SPACE_00F		0x00800000	/* initial mem space */#define BCSR0_MEM_SPACE_FF		0x01000000	/* initial mem space */#define BCSR0_MEM_SPACE_FFF		0x01800000	/* initial mem space */#define BCSR0_PCMCIA_II			0x00000000	/* Debug pins */#define BCSR0_WATCH_POINTS		0x00200000	/* Debug pins */#define BCSR0_SHOW_CYCLE		0x00600000	/* Debug pins */#define BCSR0_JTAG_PORT			0x00000000	/* debug port pins */#define BCSR0_NO_DBG_PORT		0x00080000	/* debug port pins */#define BCSR0_PCMCIA_PORT		0x00180000	/* debug port pins *//* BCSR1 bit definition (active at low level when _L) */#define BCSR1_FLASH_EN_L		0x80000000	/* Flash mem enable */#define BCSR1_DRAM_EN			0x40000000	/* Dram mem enable */#define BCSR1_ETHN_EN_L			0x20000000	/* Ethernet enable */#define BCSR1_IR_EN_L			0x10000000	/* Infra-red enable */#define BCSR1_FLCFG_EN_L		0x08000000	/* Flach config enable*/#define BCSR1_CRPROT_EN_L		0x04000000	/* Ctrl Reg protect */#define BCSR1_BCSR_EN_L			0x02000000	/* BCSR enable */#define BCSR1_RS232_EN_L		0x01000000	/* RS232 port enable */#define BCSR1_PCCARD_EN_L		0x00800000	/* PC card enable */#define BCSR1_PCCARD_VCCON_L		0x00400000	/* PC card VCC on */#define BCSR1_PCCVPP_MSK		0x00300000	/* PC card VPP */#define	BCSR1_DRAM_HALF_WORD_L		0x00080000	/* Dram half word */#define	BCSR1_RS232_2_EN_L		0x00040000	/* RS232 port 2 */#define BCSR1_SDRAM_EN                  0x00020000      /* SDRAM */#define BCSR1_RESET_VAL		(~BCSR1_DRAM_EN       & BCSR1_ETHN_EN_L   | \				 BCSR1_IR_EN_L        | BCSR1_FLCFG_EN_L  | \				 BCSR1_RS232_EN_L     | BCSR1_PCCARD_EN_L | \				 BCSR1_PCCARD_VCCON_L | BCSR1_PCCVPP_MSK  | \				 BCSR1_DRAM_HALF_WORD_L | BCSR1_RS232_2_EN_L)#define BCSR1_RESET_VAL_ENG	(BCSR1_DRAM_EN        | BCSR1_ETHN_EN_L   | \				 BCSR1_IR_EN_L        | BCSR1_FLCFG_EN_L  | \				 BCSR1_RS232_EN_L     | BCSR1_PCCARD_EN_L | \				 BCSR1_PCCARD_VCCON_L | BCSR1_PCCVPP_MSK  | \				 BCSR1_DRAM_HALF_WORD_L | BCSR1_RS232_2_EN_L)  /* BCSR2 bit definition */#define BCSR2_FLASH_PD_2MEG_SIMM	0x80000000	/* Flash presence 2 M */#define BCSR2_FLASH_PD_4MEG_SIMM	0x70000000	/* Flash presence 4 M */#define BCSR2_FLASH_PD_8MEG_SIMM	0x60000000	/* Flash presence 8 M */#define BCSR2_DRAM_EDO_L		0x00000000	/* Dram is EDO */#define BCSR2_DRAM_NO_EDO_L		0x08000000	/* Dram is not EDO */#define BCSR2_DRAM_PD_4MEG_SIMM		0x00000000	/* Dram presence  4 M */#define BCSR2_DRAM_PD_32MEG_SIMM	0x00800000	/* Dram presence 32 M */#define BCSR2_DRAM_PD_16MEG_SIMM	0x01000000	/* Dram presence 16 M */#define BCSR2_DRAM_PD_8MEG_SIMM		0x01800000	/* Dram presence  8 M */#define BCSR2_DRAM_PD_SIZE_MASK		0x01800000	/* Dram size mask */#define BCSR2_DRAM_PD_70NS_SIMM		0x04000000	/* Dram presence 70ns */#define BCSR2_DRAM_PD_60NS_SIMM		0x06000000	/* Dram presence 60ns */#define BCSR2_DRAM_PD_SPEED_MASK	0x06000000	/* Dram spreed mask *//* BCSR3 bit definition */#define BCSR3_CTR_REG_PROT_EN		0x08000000	/* Ctrl reg Protect */#define BCSR3_BREVN			0x008b0000	/* Board rev number */#define BCSR3_FLASH_PD			0x00700000	/* Flash Presence det */#define BCSR3_DBID_MASK                 0x3f000000  /* FADS daughter board id */#define BCSR3_ADS_MASK                  0x00000000  /* Mask for 8xxADS board */#define BCSR3_813DB_MASK                0x01000000  /* Mask for MPC813 db */#define BCSR3_821DB_MASK                0x02000000  /* Mask for MPC821 db */#define BCSR3_823DB_MASK                0x03000000  /* Mask for MPC823 db */#define BCSR3_801DB_MASK                0x20000000  /* Mask for MPC801 db */#define BCSR3_850DB_MASK                0x21000000  /* Mask for MPC850 db */#define BCSR3_860DB_MASK                0x22000000  /* Mask for MPC860 db */#define BCSR3_860SARDB_MASK             0x23000000  /* Mask for MPC860SAR db */#define BCSR3_860TDB_MASK               0x24000000  /* Mask for MPC860T db */#define BCSR3_850SARDB_MASK             0x3f000000  /* Mask for MPC850SAR db *//* BCSR4 bit definition */#define BCSR4_ETHLOOP                   0x80000000  /* Ethernet Loop Back */#define BCSR4_TFPLDL_L                  0x40000000  /* TP Full-Duplex */#define BCSR4_TPSQEL_L                  0x20000000  /* Signal Quality Test */#define BCSR4_SIGNAL_LAMP_L             0x10000000  /* Signal Lamp Enable Low*/#define BCSR4_MODEM_EN_L                0x00100000  /* Modem Enable on PPC823 */#define BCSR4_DATA_VOICE_L              0x00080000  /* */#define BCSR4_UUFDIS			0x08000000  /* 860T's PHY disable */#define BCSR4_FETH_CFG0			0x04000000  /* 860T's PHY conf pin 0 */#define BCSR4_FETH_FDE			0x02000000  /* 860T's PHY FD enable */#define BCSR4_FETH_CFG1			0x00400000  /* 860T's PHY conf pin 1 */#define BCSR4_FETH_RST			0x00200000  /* 860T's PHY reset *//* CPU type in the PVR */#define CPU_TYPE_860			0x0050		/* value for PPC860 */#define	CPU_REV_A1_MASK_NUM		0x0010		/* revision mask num *//* Ethernet parameters */#ifdef __cplusplus    }#endif#endif /* INCads860h */