MEMORY
{
   PAGE 0: 
           VEC1:     origin = 0080h, length = 0078h  /* Internal Program RAM */
           PRAM:     origin = 2000h, length = 2000h  /* Internal Program RAM */
           VEC2:     origin = 0xff80, length = 0x78 


   
   PAGE 1: 
           SCRATCH:  origin = 0060h, length = 0020h  /* Scratch Pad Data RAM */
           DMARAM:   origin = 0100h, length = 0400h  /* DMA buffer */
 
           STACK:    origin = 0600h, length = 0400h 
            /* Stack Memory Space   */
           EXRAM:    origin = 1100h, length = 0e00h  /* External Data RAM    */
}

/*****************************************************************************/
/* DSP Memory Allocation                                                     */
/*****************************************************************************/

SECTIONS
{
   .cinit    > PRAM  PAGE 0
   .text     > PRAM  PAGE 0
   .vectors  > VEC2  PAGE 0
   .vecs  >    VEC1  PAGE 0
   
   	
   .stack    > STACK PAGE 1
   .trap     > SCRATCH PAGE 1

   .bss      > EXRAM PAGE 1
   .cio      > EXRAM PAGE 1
   .fifo     > EXRAM PAGE 1

      

   
   audio_buffer  > DMARAM PAGE 1
   outt_buffer   > DMARAM PAGE 1 

/*   audio_buffer  > EXRAM PAGE 1
   outt_buffer   > EXRAM PAGE 1 */

   coefficients  > EXRAM   ,align (512)
   delayb         > EXRAM  ,align (512)
}