voidgen_wput(Fab *f, Reg chip[]){	Reg	*r;	putln(f,"static void\n"		"custom_wput(CPTR addr, UWORD value)\n"		"{\n"		"	switch (addr & 0xffff) {\n");	for (r = chip; r->name != NULL; r++) {		if (r->w.put != 0) {			putln(f,"	case %s:\n", r->name);			f->lvl += 2;			r->w.put(f, r);			f->lvl -= 2;			putln(f,"		break;\n");		}	}	putln(f,"	default:\n"		"		fatal();\n"		"		break;\n"		"	}\n"		"}\n"		"\n");}voidgen_lget(Fab *f, Reg chip[]){	Reg	*r;	putln(f,"static ULONG\n"		"custom_lget(CPTR addr)\n"		"{\n"		"	switch (addr & 0xffff) {\n");	for (r = chip; r->name != NULL; r++) {		if (r->l.get != 0) {			putln(f,"	case %s:\n", r->name);			f->lvl += 2;			r->l.get(f, r);			f->lvl -= 2;		}	}	putln(f,"	default:\n"		"		fatal();\n"		"		return 0;\n"		"	}\n"		"}\n"		"\n");}voidgen_lput(Fab *f, Reg chip[]){	Reg	*r;	putln(f,"static void\n"		"custom_lput(CPTR addr, ULONG value)\n"		"{\n"		"	switch (addr & 0xffff) {\n");	for (r = chip; r->name != NULL; r++) {		if (r->l.put != 0) {			putln(f,"	case %s:\n", r->name);			f->lvl += 2;			r->l.put(f, r);			f->lvl -= 2;			putln(f,"		break;\n");		}	}	putln(f,"	default:\n"		"		fatal();\n"		"		break;\n"		"	}\n"		"}\n"		"\n");}/*---------------------------------------------------------------------------* * XXX Most of this will go away as I figure out where the pieces belong *						Max Okumoto *---------------------------------------------------------------------------*/static char	*HACK[] = {"/**************************************** * Handle a key event. The fields	* * keydown and key of the shared image	* * are interpreted, and the dragonball	* * registers updated			* ****************************************/static voiddokey(void){	UBYTE		d;	d = db_PDDATA.x;	if (CustShptr->keydown) {		db_PDDATA.x |= (1 << CustShptr->key);		CustShptr->keydown = 0;		CustShptr->key = -1;	} else if (CustShptr->key >= 0) {		db_PDDATA.x &= ~(1 << CustShptr->key);		CustShptr->key = -1;	}	db_PDDATA_edge |= db_PDDATA.x & ~d;	db_IPR.anon.PEN = CustShptr->pen;	db_IPR.x = (db_IPR.x & 0xffff00ff) |		((((db_PDDATA_edge & db_PDIRQEDGE.x) |		   (db_PDDATA.x & ~db_PDIRQEDGE.x)) & db_PDIRQEN.x) << 8);}voidupdateisr(){	db_IPR.anon.PEN = CustShptr->pen;	db_ISR.x = db_IPR.x & ~db_IMR.x;	if (db_ISR.x) {		specialflags |= SPCFLAG_INT;	}	CustShptr->run_updateisr = 0;}voidmaybe_updateisr(){	if (CustShptr->run_updateisr) {		dokey();		updateisr();	}}intintbase(){	return db_IVR.anon.VECTOR << 3;}intintlev(){	if (db_ISR.anon.IRQ7)	return 7;	if (db_ISR.anon.SPIS)	return 6;	if (db_ISR.anon.TMR1)	return 6;	if (db_ISR.anon.IRQ6)	return 6;	if (db_ISR.anon.PEN)	return 5;	if (db_ISR.anon.SPIM)	return 4;	if (db_ISR.anon.TMR2)	return 4;	if (db_ISR.anon.UART)	return 4;	if (db_ISR.anon.WDT)	return 4;	if (db_ISR.anon.RTC)	return 4;	if (db_ISR.anon.KB)	return 4;	if (db_ISR.anon.PWM)	return 4;	if (db_ISR.anon.INT0)	return 4;	if (db_ISR.anon.INT1)	return 4;	if (db_ISR.anon.INT2)	return 4;	if (db_ISR.anon.INT3)	return 4;	if (db_ISR.anon.INT4)	return 4;	if (db_ISR.anon.INT5)	return 4;	if (db_ISR.anon.INT6)	return 4;	if (db_ISR.anon.INT7)	return 4;	if (db_ISR.anon.IRQ3)	return 3;	if (db_ISR.anon.IRQ2)	return 2;	if (db_ISR.anon.IRQ1)	return 1;	return -1;}static voidpen(int down, int x, int y){	if (!pendown && down) {		db_IPR.anon.PEN = 1;		updateisr();	} else if (pendown && !down) {		db_IPR.anon.PEN = 0;		updateisr();	}	pendown = down;	penx = x;	peny = y;}static voidhotsync(int down){	if (down) {		db_IPR.anon.IRQ1 = 1;	} else {		db_IPR.anon.IRQ1 = 0;	}	updateisr();}/* * custptr is a pointer to a shared memory block which will \"back-up\" * the register values of the custom circuits, allowing other processes * to look at register values */voidcustom_init(shared_img * shptr){	CustShptr = shptr;	CustShptr->PICF = 0;	CustShptr->VPW = 0xff;	CustShptr->POSR = 0;	CustShptr->grpalette[0] = 1;	CustShptr->grpalette[1] = 0;	CustShptr->grpalette[2] = 3;	CustShptr->grpalette[3] = 7;	CustShptr->quit = 0;	CustShptr->run_updateisr = 0;	CustShptr->LcdPower = lcdOn;	CustShptr->Backlight = 0;	customreset();}voiddo_cycles(int longtime){	if (db_TCTL2.anon.TEN) {		db_TCN2.anon.COUNT++;		if (db_TCN2.anon.COUNT > db_TCMP2.anon.COMPARE || longtime) {			db_TSTAT2.anon.COMP = 1;			if (db_TCTL2.anon.FRR == 0) {				db_TCN2.anon.COUNT = 0;			}			if (db_TCTL2.anon.IRQEN) {				db_IPR.anon.TMR2 = 1;				updateisr();			}		}	}	/*	 * Determine if there are any chars to read from the serial port or	 * debugger	 */	/*	 * WARNING: This uses a shared memory data structure to store the	 * FIFO. The producer is adding things to this _at the same time_ as	 * this is consuming.  Examine main.c and take a course in concurrent	 * programming before modifying this.  :-) - Ian	 */	if (CustShptr->serial.head != CustShptr->serial.tail &&	    db_USTCNT.anon.UART_ENABLE && !db_URX.anon.DATA_READY) {		int	curhead = CustShptr->serial.head;		db_URX.anon.DATA = CustShptr->serial.fifo[curhead];		curhead += 1;		if (curhead == FIFO_SIZE) {			curhead = 0;		}		CustShptr->serial.head = curhead;		db_URX.anon.DATA_READY = 1;		if (db_USTCNT.anon.RX_READY_ENABLE) {			db_IPR.anon.UART = 1;			updateisr();		}	}	if (CustShptr->gdb.head != CustShptr->gdb.tail &&	    db_USTCNT.anon.UART_ENABLE && !db_URXdb.anon.DATA_READY) {		int	curhead = CustShptr->gdb.head;		db_URXdb.anon.DATA = CustShptr->gdb.fifo[curhead];		curhead += 1;		if (curhead == FIFO_SIZE) {			curhead = 0;		}		CustShptr->gdb.head = curhead;		db_URXdb.anon.DATA_READY = 1;	}}struct EventType {	UWORD	eType;	UWORD	penDown;	UWORD	screenX;	UWORD	screenY;	UWORD	data[8];};struct SndCommandType {	UWORD	cmd;	UWORD	param1hi;	UWORD	param1lo;	UWORD	param2;	UWORD	param3;};#define keyDownEvent		4#define sysTrapEvtGetEvent	41245#define sysTrapSndDoCmd		41523intdo_api(int api){	switch (api) {		case sysTrapEvtGetEvent:		if (CustShptr->kbin != CustShptr->kbout) {			struct EventType	*ev;			int			out;			out = CustShptr->kbout;			ev = (struct EventType *) get_real_address(get_long(CustShptr->regs.a[7]));			ev->eType = keyDownEvent;			ev->data[0] = CustShptr->kb[out];			ev->data[1] = 0;			ev->data[2] = 0;			CustShptr->kbout = (out + 1) & 7;			return 1;		}		break;	case sysTrapSndDoCmd:		{			struct SndCommandType *sc;			sc = (struct SndCommandType *)				get_real_address(get_long(CustShptr->regs.a[7] + 4));			if ((sc->cmd >> 8) == 1) {				CustShptr->BellFreq = (sc->param1hi << 16) + sc->param1lo;				CustShptr->BellDur = sc->param2;				CustShptr->BellAmp = sc->param3;				CustShptr->LcdReq = lcdBell;				return 1;			}		}		break;	}	return 0;}"};/*---------------------------------------------------------------------------* * Hardware description *---------------------------------------------------------------------------*/static Reg dragonball[] = {	/* System Control */	{"SCR",		0xF000, 1, 0x0c, /* System Control Reg */		{reg_get, scr_put}, {0, 0}, {0, 0},		"WDTH8:1;RSVD:1;DMAP:1;SO:1;BETEN:1;PRV:1;WPV:1;BETO:1;"},#if NOT_IMPL	{"MRR",		0xF004, 4, 0x00, /* Mask Revision Reg */		{0, 0}, {0, 0}, {0, 0},		""},#endif	/* Chip Select */	{"GRPBASEA",	0xF100, 2, 0x0000, /* Chip Select Group A Base Reg */		{0, 0}, {reg_get, reg_put}, {0, 0},		"V:1;:3;GMA:12;"},#if NOT_IMPL	{"GRPBASEB",	0xF102, 2, 0x0000, /* Chip Select Group B Base Reg */		{0, 0}, {0, 0}, {0, 0},		"V:1;:3;GMA:12;"},#endif	{"GRPBASEC",	0xF104, 2, 0x0000, /* Chip Select Group C Base Reg */		{0, 0}, {reg_get, reg_put}, {0, 0},		"V:1;:3;GMA:12;"},#if NOT_IMPL	{"GRPBASED",	0xF106, 2, 0x0000, /* Chip Select Group D Base Reg */		{0, 0}, {0, 0}, {0, 0},		"V:1;:3;GMA:12;"},#endif	{"GRPMASKA",	0xF108, 2, 0x0000, /* Chip Select Group A Mask Reg */		{0, 0}, {reg_get, reg_put}, {0, 0},		":4;GMA:12;"},#if NOT_IMPL	{"GRPMASKB",	0xF10A, 2, 0x0000, /* Chip Select Group B Mask Reg */		{0, 0}, {0, 0}, {0, 0},		":4;GMA:12;"},#endif	{"GRPMASKC",	0xF10C, 2, 0x0000, /* Chip Select Group C Mask Reg */		{0, 0}, {reg_get, reg_put}, {0, 0},		":4;GMA:12;"},#if NOT_IMPL	{"GRPMASKD",	0xF10E, 2, 0x0000, /* Chip Select Group D Mask Reg */		{0, 0}, {0, 0}, {0, 0},		":4;GMA:12;"},#endif	{"CSA0",	0xF110, 4, 0x00010006, /* Group A Chip Select 0 Reg */		{0, 0}, {0, 0}, {reg_get, reg_put},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSA1",	0xF114, 4, 0x00010006, /* Group A Chip Select 1 Reg */		{0, 0}, {0, 0}, {reg_get, csa1_put},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSA2",	0xF118, 4, 0x00010006, /* Group A Chip Select 2 Reg */		{0, 0}, {0, 0}, {reg_get, reg_put},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSA3",	0xF11C, 4, 0x00010006, /* Group A Chip Select 3 Reg */		{0, 0}, {0, 0}, {reg_get, reg_put},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},#if NOT_IMPL	{"CSB0",	0xF120, 4, 0x00010006, /* Group B Chip Select 0 Reg */		{0, 0}, {0, 0}, {0, 0},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSB1",	0xF124, 4, 0x00010006, /* Group B Chip Select 1 Reg */		{0, 0}, {0, 0}, {0, 0},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSB2",	0xF128, 4, 0x00010006, /* Group B Chip Select 2 Reg */		{0, 0}, {0, 0}, {0, 0},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSB3",	0xF12C, 4, 0x00010006, /* Group B Chip Select 3 Reg */		{0, 0}, {0, 0}, {0, 0},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},#endif	{"CSC0",	0xF130, 4, 0x00010006, /* Group C Chip Select 0 Reg */		{0, 0}, {0, 0}, {reg_get, reg_put},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSC1",	0xF134, 4, 0x00010006, /* Group C Chip Select 1 Reg */		{0, 0}, {0, 0}, {reg_get, reg_put},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSC2",	0xF138, 4, 0x00010006, /* Group C Chip Select 2 Reg */		{0, 0}, {0, 0}, {reg_get, reg_put},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSC3",	0xF13C, 4, 0x00010006, /* Group C Chip Select 3 Reg */		{0, 0}, {0, 0}, {reg_get, reg_put},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},#if NOT_IMPL	{"CSD0",	0xF140, 4, 0x00010006, /* Group D Chip Select 0 Reg */		{0, 0}, {0, 0}, {0, 0},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSD1",	0xF144, 4, 0x00010006, /* Group D Chip Select 1 Reg */		{0, 0}, {0, 0}, {0, 0},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSD2",	0xF148, 4, 0x00010006, /* Group D Chip Select 2 Reg */		{0, 0}, {0, 0}, {0, 0},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},	{"CSD3",	0xF14C, 4, 0x00010006, /* Group D Chip Select 3 Reg */		{0, 0}, {0, 0}, {0, 0},		"WAIT:3;RO:1;:4;AM:8;BSW:1;:7;AC:8;"},#endif	/* Phase Locked Loop */	{"PLLCR",	0xF200, 2, 0x2400, /* PLL Control Reg */		{0, 0}, {reg_get, reg_put}, {0, 0},		":3;DISPLL:1;CLKEN:1;:3;SYSCLKSEL:3;PIXCLKSEL:3;:2;"},	{"PLLFSR",	0xF202, 2, 0x0123, /* PLL Frequency Select Reg */		{0, 0}, {pllfsr_get, reg_put}, {0, 0},		"PC:8;QC:4;:2;PROT:1;CLK32:1;"},	{"PCTLR",	0xF207, 1, 0x1f, /* Power Control Reg */		{reg_get, reg_put}, {0, 0}, {0, 0},		"WIDTH:5;:1;STOP:1;PCEN:1;"},	/* Interrupt controller */	{"IVR",		0xF300, 1, 0x00, /* Interrupt Vector Reg */		{reg_get, reg_put}, {0, 0}, {0, 0},		"LEVEL:3;VECTOR:5;"},	{"ICR",		0xF302, 2, 0x0000, /* Interrupt Control Reg */		{0, 0}, {reg_get, reg_put}, {0, 0},		":8;POL6:1;POL3:1;POL2:1;POL1:1;ET6:1;ET3:1;ET2:1;ET1:1;"},	{"IMR",		0xF304, 4, 0x00ffffff, /* Interrupt Mask Reg */		{0, 0}, {imr_get_xxx, imr_put_xxx}, {reg_get, imr_put},		"SPIM:1;TMR2:1;UART:1;WDT:1;RTC:1;LCDC:1;KB:1;PWM:1;INT0:1;INT1:1;INT2:1;INT3:1;INT4:1;INT5:1;INT6:1;INT7:1;IRQ1:1;IRQ2:1;IRQ3:1;IRQ6:1;PEN:1;SPIS:1;TMR1:1;IRQ7:1;:8;"},	{"IWR",		0xF308, 4, 0x00ffffff, /* Interrupt Wakeup Enable Reg */		{0, 0}, {iwr_get_xxx, iwr_put_xxx}, {reg_get, reg_put},		"SPIM:1;TMR2:1;UART:1;WDT:1;RTC:1;LCDC:1;KB:1;PWM:1;INT0:1;INT1:1;INT2:1;INT3:1;INT4:1;INT5:1;INT6:1;INT7:1;IRQ1:1;IRQ2:1;IRQ3:1;IRQ6:1;PEN:1;SPIS:1;TMR1:1;IRQ7:1;:8;"},	{"ISR",		0xF30C, 4, 0x00000000, /* Interrupt Status Reg */		{0, 0}, {isr_get_xxx, isr_put_xxx}, {reg_get, isr_put},		"SPIM:1;TMR2:1;UART:1;WDT:1;RTC:1;LCDC:1;KB:1;PWM:1;INT0:1;INT1:1;INT2:1;INT3:1;INT4:1;INT5:1;INT6:1;INT7:1;IRQ1:1;IRQ2:1;IRQ3:1;IRQ6:1;PEN:1;SPIS:1;TMR1:1;IRQ7:1;:8;"},	{"IPR",		0xF310, 4, 0x00000000, /* Interrupt Pending Reg */		{0, 0}, {ipr_get_xxx, 0}, {ipr_get, ipr_put},		"SPIM:1;TMR2:1;UART:1;WDT:1;RTC:1;LCDC:1;KB:1;PWM:1;INT0:1;INT1:1;INT2:1;INT3:1;INT4:1;INT5:1;INT6:1;INT7:1;IRQ1:1;IRQ2:1;IRQ3:1;IRQ6:1;PEN:1;SPIS:1;TMR1:1;IRQ7:1;:8;"},	/* Parallel IO */#if NOT_IMPL