Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1624
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
pc2fpga
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|Src|pc2fpga.v
1115480140
7
# storage
db|pc2fpga.(0).cnf
db|pc2fpga.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
IDLE
000
PARAMETER_BIN
DEF
READ_1
001
PARAMETER_BIN
DEF
READ_2
010
PARAMETER_BIN
DEF
}
# hierarchies {
|
}
# end
# entity
sld_signaltap
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_signaltap.vhd
1114066240
4
# storage
db|pc2fpga.(1).cnf
db|pc2fpga.(1).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
402681344
PARAMETER_UNKNOWN
USR
sld_ip_version
3
PARAMETER_DEC
DEF
sld_ip_minor_version
2
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
sld_data_bits
14
PARAMETER_UNKNOWN
USR
sld_trigger_bits
14
PARAMETER_UNKNOWN
USR
sld_data_bit_cntr_bits
4
PARAMETER_UNKNOWN
USR
sld_node_crc_bits
32
PARAMETER_DEC
DEF
sld_node_crc_hiword
9249
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
17823
PARAMETER_UNKNOWN
USR
sld_incremental_routing
0
PARAMETER_DEC
DEF
sld_sample_depth
1024
PARAMETER_UNKNOWN
USR
sld_mem_address_bits
10
PARAMETER_UNKNOWN
USR
sld_ram_block_type
AUTO
PARAMETER_STRING
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
1
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_2
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_3
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_4
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_5
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_6
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_7
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_8
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_9
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_10
NONE
PARAMETER_STRING
DEF
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|sld_signaltap.vhd
1114066240
}
# end
# entity
sld_ela_control
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_ela_control.vhd
1114066238
4
# storage
db|pc2fpga.(2).cnf
db|pc2fpga.(2).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
trigger_input_width
14
PARAMETER_DEC
USR
trigger_level
1
PARAMETER_DEC
USR
trigger_in_enabled
1
PARAMETER_DEC
USR
enable_clk_edge_def
0
PARAMETER_DEC
USR
enable_async_glitch
0
PARAMETER_DEC
USR
enable_sync_normal
1
PARAMETER_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_DEC
USR
trigger_level_pipeline
1
PARAMETER_DEC
USR
ela_status_bits
3
PARAMETER_DEC
USR
mem_address_bits
10
PARAMETER_DEC
USR
sample_depth
1024
PARAMETER_DEC
USR
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114066454
6
# storage
db|pc2fpga.(3).cnf
db|pc2fpga.(3).cnf
# user_parameter {
LPM_WIDTH
19
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data15
data16
data17
data18
data1
data2
data3
data4
data5
data6
data7
data8
data9
enable
load
q0
q10
q11
q12
q13
q14
q15
q16
q17
q18
q1
q2
q3
q4
q5
q6
q7
q8
q9
shiftin
shiftout
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107628524
c:|altera|quartus50|libraries|megafunctions|dffeea.inc
1107628164
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114066420
}
# end
# entity
sld_ela_basic_multi_level_trigger
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_ela_control.vhd
1114066238
4
# storage
db|pc2fpga.(4).cnf
db|pc2fpga.(4).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
trigger_level
1
PARAMETER_DEC
USR
data_bits
14
PARAMETER_DEC
USR
async_enabled
0
PARAMETER_DEC
USR
sync_enabled
1
PARAMETER_DEC
USR
pipeline
1
PARAMETER_DEC
USR
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114066454
6
# storage
db|pc2fpga.(5).cnf
db|pc2fpga.(5).cnf
# user_parameter {
LPM_WIDTH
42
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data1
data20
data21
data22
data23
data24
data25
data26
data27
data28
data29
data2
data30
data31
data32
data33
data34
data35
data36
data37
data38
data39
data3
data40
data41
data4
data5
data6
data7
data8
data9
enable
load
q0
q10
q11
q12
q13
q14
q15
q16
q17
q18
q19
q1
q20
q21
q22
q23
q24
q25
q26
q27
q28
q29
q2
q30
q31
q32
q33
q34
q35
q36
q37
q38
q39
q3
q40
q41
q4
q5
q6
q7
q8
q9
shiftin
shiftout
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107628524
c:|altera|quartus50|libraries|megafunctions|dffeea.inc
1107628164
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114066420
}
# end
# entity
sld_mbpmg
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_mbpmg.vhd
1114066238
4
# storage
db|pc2fpga.(6).cnf
db|pc2fpga.(6).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
data_bits
14
PARAMETER_DEC
USR
pattern_bits
3
PARAMETER_DEC
USR
async_enabled
0
PARAMETER_DEC
USR
sync_enabled
1
PARAMETER_DEC
USR
pipeline
1
PARAMETER_DEC
USR
}
# end
# entity
sld_sbpmg
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_mbpmg.vhd
1114066238
4
# storage
db|pc2fpga.(7).cnf
db|pc2fpga.(7).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
async_enabled
0
PARAMETER_DEC
USR
pipeline
1
PARAMETER_DEC
USR
}
# end
# entity
sld_mbpmg
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_mbpmg.vhd
1114066238
4
# storage
db|pc2fpga.(8).cnf
db|pc2fpga.(8).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
data_bits
1
PARAMETER_DEC
USR
pattern_bits
3
PARAMETER_DEC
USR
async_enabled
0
PARAMETER_DEC
USR
sync_enabled
1
PARAMETER_DEC
USR
pipeline
1
PARAMETER_DEC
DEF
}
# end
# entity
sld_ela_level_seq_mgr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_ela_control.vhd
1114066238
4
# storage
db|pc2fpga.(9).cnf
db|pc2fpga.(9).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
trigger_level
2
PARAMETER_DEC
USR
ela_status_bits
3
PARAMETER_DEC
USR
mem_address_bits
10
PARAMETER_DEC
USR
trigger_in_enabled
1
PARAMETER_DEC
USR
}
# end
# entity
sld_ela_state_machine
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_ela_control.vhd
1114066238
4
# storage
db|pc2fpga.(10).cnf
db|pc2fpga.(10).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
}
# end
# entity
sld_ela_seg_state_machine
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_ela_control.vhd
1114066238
4
# storage
db|pc2fpga.(11).cnf
db|pc2fpga.(11).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
ela_status_bits
3
PARAMETER_DEC
USR
}
# end
# entity
sld_ela_post_trigger_counter
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_ela_control.vhd
1114066238
4
# storage
db|pc2fpga.(12).cnf
db|pc2fpga.(12).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version