{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 27 23:34:01 2005 " "Info: Processing started: Mon Jun 27 23:34:01 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off ColorBar -c ColorBar --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ColorBar -c ColorBar --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "vga_blue:inst\|hsyncint " "Info: Detected ripple clock \"vga_blue:inst\|hsyncint\" as buffer" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 88 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "vga_blue:inst\|hsyncint" } } } }  } 0}  } {  } 0}