?? colorbar.tan.qmsg
字號:
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 register vga_blue:inst\|vcnt\[3\] register vga_blue:inst\|enable 2.627 ns " "Info: Slack time is 2.627 ns for clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" between source register \"vga_blue:inst\|vcnt\[3\]\" and destination register \"vga_blue:inst\|enable\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "50.64 MHz 19.746 ns " "Info: Fmax is 50.64 MHz (period= 19.746 ns)" { } { } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "6.309 ns + Largest register register " "Info: + Largest register to register requirement is 6.309 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "12.500 ns + " "Info: + Setup relationship between source and destination is 12.500 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 22.946 ns " "Info: + Latch edge is 22.946 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns -2.054 ns 50 " "Info: Clock period of Destination clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with offset of -2.054 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 10.446 ns " "Info: - Launch edge is 10.446 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns 10.446 ns , Inverted 50 " "Info: Clock period of Source clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with , Inverted offset of 10.446 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.930 ns + Largest " "Info: + Largest clock skew is -5.930 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 destination 2.464 ns + Shortest register " "Info: + Shortest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to destination register is 2.464 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.753 ns) + CELL(0.711 ns) 2.464 ns vga_blue:inst\|enable 2 REG LC_X32_Y22_N2 1 " "Info: 2: + IC(1.753 ns) + CELL(0.711 ns) = 2.464 ns; Loc. = LC_X32_Y22_N2; Fanout = 1; REG Node = 'vga_blue:inst\|enable'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|enable } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 88 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 28.86 % " "Info: Total cell delay = 0.711 ns ( 28.86 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.753 ns 71.14 % " "Info: Total interconnect delay = 1.753 ns ( 71.14 % )" { } { } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|enable } { 0.000ns 1.753ns } { 0.000ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 source 8.394 ns - Longest register " "Info: - Longest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 8.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.744 ns) + CELL(0.935 ns) 2.679 ns vga_blue:inst\|hsyncint 2 REG LC_X31_Y13_N2 13 " "Info: 2: + IC(1.744 ns) + CELL(0.935 ns) = 2.679 ns; Loc. = LC_X31_Y13_N2; Fanout = 13; REG Node = 'vga_blue:inst\|hsyncint'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "2.679 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 88 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.004 ns) + CELL(0.711 ns) 8.394 ns vga_blue:inst\|vcnt\[3\] 3 REG LC_X31_Y23_N8 5 " "Info: 3: + IC(5.004 ns) + CELL(0.711 ns) = 8.394 ns; Loc. = LC_X31_Y23_N8; Fanout = 5; REG Node = 'vga_blue:inst\|vcnt\[3\]'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "5.715 ns" { vga_blue:inst|hsyncint vga_blue:inst|vcnt[3] } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 87 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 19.61 % " "Info: Total cell delay = 1.646 ns ( 19.61 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.748 ns 80.39 % " "Info: Total interconnect delay = 6.748 ns ( 80.39 % )" { } { } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[3] } { 0.000ns 1.744ns 5.004ns } { 0.000ns 0.935ns 0.711ns } } } } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|enable } { 0.000ns 1.753ns } { 0.000ns 0.711ns } } } { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[3] } { 0.000ns 1.744ns 5.004ns } { 0.000ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 87 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 88 -1 0 } } } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|enable } { 0.000ns 1.753ns } { 0.000ns 0.711ns } } } { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[3] } { 0.000ns 1.744ns 5.004ns } { 0.000ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.682 ns - Longest register register " "Info: - Longest register to register delay is 3.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_blue:inst\|vcnt\[3\] 1 REG LC_X31_Y23_N8 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y23_N8; Fanout = 5; REG Node = 'vga_blue:inst\|vcnt\[3\]'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "" { vga_blue:inst|vcnt[3] } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 87 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.283 ns) + CELL(0.590 ns) 1.873 ns vga_blue:inst\|always4~159 2 COMB LC_X32_Y22_N7 2 " "Info: 2: + IC(1.283 ns) + CELL(0.590 ns) = 1.873 ns; Loc. = LC_X32_Y22_N7; Fanout = 2; COMB Node = 'vga_blue:inst\|always4~159'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "1.873 ns" { vga_blue:inst|vcnt[3] vga_blue:inst|always4~159 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.432 ns) + CELL(0.590 ns) 2.895 ns vga_blue:inst\|always4~162 3 COMB LC_X32_Y22_N0 1 " "Info: 3: + IC(0.432 ns) + CELL(0.590 ns) = 2.895 ns; Loc. = LC_X32_Y22_N0; Fanout = 1; COMB Node = 'vga_blue:inst\|always4~162'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "1.022 ns" { vga_blue:inst|always4~159 vga_blue:inst|always4~162 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.191 ns vga_blue:inst\|always4~163 4 COMB LC_X32_Y22_N1 1 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 3.191 ns; Loc. = LC_X32_Y22_N1; Fanout = 1; COMB Node = 'vga_blue:inst\|always4~163'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "0.296 ns" { vga_blue:inst|always4~162 vga_blue:inst|always4~163 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 3.682 ns vga_blue:inst\|enable 5 REG LC_X32_Y22_N2 1 " "Info: 5: + IC(0.182 ns) + CELL(0.309 ns) = 3.682 ns; Loc. = LC_X32_Y22_N2; Fanout = 1; REG Node = 'vga_blue:inst\|enable'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "0.491 ns" { vga_blue:inst|always4~163 vga_blue:inst|enable } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 88 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.603 ns 43.54 % " "Info: Total cell delay = 1.603 ns ( 43.54 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.079 ns 56.46 % " "Info: Total interconnect delay = 2.079 ns ( 56.46 % )" { } { } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "3.682 ns" { vga_blue:inst|vcnt[3] vga_blue:inst|always4~159 vga_blue:inst|always4~162 vga_blue:inst|always4~163 vga_blue:inst|enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.682 ns" { vga_blue:inst|vcnt[3] vga_blue:inst|always4~159 vga_blue:inst|always4~162 vga_blue:inst|always4~163 vga_blue:inst|enable } { 0.000ns 1.283ns 0.432ns 0.182ns 0.182ns } { 0.000ns 0.590ns 0.590ns 0.114ns 0.309ns } } } } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|enable } { 0.000ns 1.753ns } { 0.000ns 0.711ns } } } { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[3] } { 0.000ns 1.744ns 5.004ns } { 0.000ns 0.935ns 0.711ns } } } { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "3.682 ns" { vga_blue:inst|vcnt[3] vga_blue:inst|always4~159 vga_blue:inst|always4~162 vga_blue:inst|always4~163 vga_blue:inst|enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.682 ns" { vga_blue:inst|vcnt[3] vga_blue:inst|always4~159 vga_blue:inst|always4~162 vga_blue:inst|always4~163 vga_blue:inst|enable } { 0.000ns 1.283ns 0.432ns 0.182ns 0.182ns } { 0.000ns 0.590ns 0.590ns 0.114ns 0.309ns } } } } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" { } { } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 register vga_blue:inst\|vcnt\[10\] register vga_blue:inst\|vcnt\[10\] 1.073 ns " "Info: Minimum slack time is 1.073 ns for clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" between source register \"vga_blue:inst\|vcnt\[10\]\" and destination register \"vga_blue:inst\|vcnt\[10\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.864 ns + Shortest register register " "Info: + Shortest register to register delay is 0.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_blue:inst\|vcnt\[10\] 1 REG LC_X31_Y22_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y22_N5; Fanout = 4; REG Node = 'vga_blue:inst\|vcnt\[10\]'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "" { vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 87 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.309 ns) 0.864 ns vga_blue:inst\|vcnt\[10\] 2 REG LC_X31_Y22_N5 4 " "Info: 2: + IC(0.555 ns) + CELL(0.309 ns) = 0.864 ns; Loc. = LC_X31_Y22_N5; Fanout = 4; REG Node = 'vga_blue:inst\|vcnt\[10\]'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "0.864 ns" { vga_blue:inst|vcnt[10] vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 87 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 35.76 % " "Info: Total cell delay = 0.309 ns ( 35.76 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.555 ns 64.24 % " "Info: Total interconnect delay = 0.555 ns ( 64.24 % )" { } { } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "0.864 ns" { vga_blue:inst|vcnt[10] vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.864 ns" { vga_blue:inst|vcnt[10] vga_blue:inst|vcnt[10] } { 0.0ns 0.555ns } { 0.0ns 0.309ns } } } } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.446 ns " "Info: + Latch edge is 10.446 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns 10.446 ns , Inverted 50 " "Info: Clock period of Destination clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with , Inverted offset of 10.446 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 10.446 ns " "Info: - Launch edge is 10.446 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns 10.446 ns , Inverted 50 " "Info: Clock period of Source clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with , Inverted offset of 10.446 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 destination 8.394 ns + Longest register " "Info: + Longest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to destination register is 8.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.744 ns) + CELL(0.935 ns) 2.679 ns vga_blue:inst\|hsyncint 2 REG LC_X31_Y13_N2 13 " "Info: 2: + IC(1.744 ns) + CELL(0.935 ns) = 2.679 ns; Loc. = LC_X31_Y13_N2; Fanout = 13; REG Node = 'vga_blue:inst\|hsyncint'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "2.679 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 88 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.004 ns) + CELL(0.711 ns) 8.394 ns vga_blue:inst\|vcnt\[10\] 3 REG LC_X31_Y22_N5 4 " "Info: 3: + IC(5.004 ns) + CELL(0.711 ns) = 8.394 ns; Loc. = LC_X31_Y22_N5; Fanout = 4; REG Node = 'vga_blue:inst\|vcnt\[10\]'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "5.715 ns" { vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 87 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 19.61 % " "Info: Total cell delay = 1.646 ns ( 19.61 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.748 ns 80.39 % " "Info: Total interconnect delay = 6.748 ns ( 80.39 % )" { } { } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } { 0.0ns 1.744ns 5.004ns } { 0.0ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 source 8.394 ns - Shortest register " "Info: - Shortest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 8.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.744 ns) + CELL(0.935 ns) 2.679 ns vga_blue:inst\|hsyncint 2 REG LC_X31_Y13_N2 13 " "Info: 2: + IC(1.744 ns) + CELL(0.935 ns) = 2.679 ns; Loc. = LC_X31_Y13_N2; Fanout = 13; REG Node = 'vga_blue:inst\|hsyncint'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "2.679 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 88 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.004 ns) + CELL(0.711 ns) 8.394 ns vga_blue:inst\|vcnt\[10\] 3 REG LC_X31_Y22_N5 4 " "Info: 3: + IC(5.004 ns) + CELL(0.711 ns) = 8.394 ns; Loc. = LC_X31_Y22_N5; Fanout = 4; REG Node = 'vga_blue:inst\|vcnt\[10\]'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "5.715 ns" { vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 87 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 19.61 % " "Info: Total cell delay = 1.646 ns ( 19.61 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.748 ns 80.39 % " "Info: Total interconnect delay = 6.748 ns ( 80.39 % )" { } { } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } { 0.0ns 1.744ns 5.004ns } { 0.0ns 0.935ns 0.711ns } } } } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } { 0.0ns 1.744ns 5.004ns } { 0.0ns 0.935ns 0.711ns } } } { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } { 0.0ns 1.744ns 5.004ns } { 0.0ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 87 -1 0 } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 87 -1 0 } } } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } { 0.0ns 1.744ns 5.004ns } { 0.0ns 0.935ns 0.711ns } } } { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } { 0.0ns 1.744ns 5.004ns } { 0.0ns 0.935ns 0.711ns } } } } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "0.864 ns" { vga_blue:inst|vcnt[10] vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.864 ns" { vga_blue:inst|vcnt[10] vga_blue:inst|vcnt[10] } { 0.0ns 0.555ns } { 0.0ns 0.309ns } } } { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } { 0.0ns 1.744ns 5.004ns } { 0.0ns 0.935ns 0.711ns } } } { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vcnt[10] } { 0.0ns 1.744ns 5.004ns } { 0.0ns 0.935ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk VGA_VS vga_blue:inst\|vsync 13.548 ns register " "Info: tco from clock \"clk\" to destination pin \"VGA_VS\" through register \"vga_blue:inst\|vsync\" is 13.548 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk VGA_PLL:inst4\|altpll:altpll_component\|_clk0 -2.054 ns + " "Info: + Offset between input clock \"clk\" and output clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is -2.054 ns" { } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 24 104 272 40 "clk" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 source 8.394 ns + Longest register " "Info: + Longest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 8.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.744 ns) + CELL(0.935 ns) 2.679 ns vga_blue:inst\|hsyncint 2 REG LC_X31_Y13_N2 13 " "Info: 2: + IC(1.744 ns) + CELL(0.935 ns) = 2.679 ns; Loc. = LC_X31_Y13_N2; Fanout = 13; REG Node = 'vga_blue:inst\|hsyncint'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "2.679 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 88 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.004 ns) + CELL(0.711 ns) 8.394 ns vga_blue:inst\|vsync 3 REG LC_X31_Y22_N8 1 " "Info: 3: + IC(5.004 ns) + CELL(0.711 ns) = 8.394 ns; Loc. = LC_X31_Y22_N8; Fanout = 1; REG Node = 'vga_blue:inst\|vsync'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "5.715 ns" { vga_blue:inst|hsyncint vga_blue:inst|vsync } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 65 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 19.61 % " "Info: Total cell delay = 1.646 ns ( 19.61 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.748 ns 80.39 % " "Info: Total interconnect delay = 6.748 ns ( 80.39 % )" { } { } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vsync } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vsync } { 0.000ns 1.744ns 5.004ns } { 0.000ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 65 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.984 ns + Longest register pin " "Info: + Longest register to pin delay is 6.984 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_blue:inst\|vsync 1 REG LC_X31_Y22_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y22_N8; Fanout = 1; REG Node = 'vga_blue:inst\|vsync'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "" { vga_blue:inst|vsync } "NODE_NAME" } "" } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 65 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.860 ns) + CELL(2.124 ns) 6.984 ns VGA_VS 2 PIN PIN_141 0 " "Info: 2: + IC(4.860 ns) + CELL(2.124 ns) = 6.984 ns; Loc. = PIN_141; Fanout = 0; PIN Node = 'VGA_VS'" { } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "6.984 ns" { vga_blue:inst|vsync VGA_VS } "NODE_NAME" } "" } } { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 256 608 784 272 "VGA_VS" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 30.41 % " "Info: Total cell delay = 2.124 ns ( 30.41 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.860 ns 69.59 % " "Info: Total interconnect delay = 4.860 ns ( 69.59 % )" { } { } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "6.984 ns" { vga_blue:inst|vsync VGA_VS } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.984 ns" { vga_blue:inst|vsync VGA_VS } { 0.000ns 4.860ns } { 0.000ns 2.124ns } } } } 0} } { { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vsync } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.394 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_blue:inst|hsyncint vga_blue:inst|vsync } { 0.000ns 1.744ns 5.004ns } { 0.000ns 0.935ns 0.711ns } } } { "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/" "" "6.984 ns" { vga_blue:inst|vsync VGA_VS } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.984 ns" { vga_blue:inst|vsync VGA_VS } { 0.000ns 4.860ns } { 0.000ns 2.124ns } } } } 0}
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