library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count is
port( clk:in std_logic;
      t1a: in std_logic;
      start:in std_logic;
      finish:out std_logic;
      ini : in std_logic_vector(7 downto 0);
      show: out std_logic_vector(7 downto 0);
      enter:in std_logic
     );
end entity count;
architecture five of count is 
signal fini:std_logic;
signal show1 :std_logic_vector(7 downto 0);
begin 
process(t1a,clk,start)
variable num : std_logic_vector(7 downto 0):="11111111";
begin
if enter='1' then num:=ini;
elsif (t1a'event and t1a='1' and start='1' and num/=0) then num:=num-1;
end if;
if num=0 then fini<='1';num:="00000000";
else fini<='0';
end if;
show1<=num;
end process ;
process(clk)
begin
if clk'event and clk='1' then finish<=fini;show<=show1;
end if;
end process;
end ;