library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count is
port( --clk:in std_logic;
      t1a: in std_logic;
      start:in std_logic;
      finish:out std_logic;
      ini : in std_logic_vector(7 downto 0);
      show: out std_logic_vector(7 downto 0)
     );
end entity count;
architecture five of count is 
signal sta : std_logic_vector(1 downto 0):="00";
begin 
process(t1a,start)
variable  num : std_logic_vector(7 downto 0):="11111111";
begin 
if sta="00" and start='0' then num:=ini;sta<="01";finish<='0';
elsif (start='1'  and sta="01" and num/=0)then num:=num-1;
end if;
if (start='1' and num=0 ) then finish<='1';sta<="10";
end if;
if sta="10" then num:="00000000";finish<='1';
end if;
show<=num;
end process ;
end ;