library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity PSK is
   port(clk,enable:in std_logic;
		x: in std_logic_vector(11 downto 0);
        q:out std_logic_vector(11 downto 0));
end PSK;
architecture behav of PSK IS
begin
process(clk,enable)
  begin
    if clk='1' then
	     if enable='1' then
            q<=not x;
         
	     end if;
    else q<=x;
	end if;
end process;    
end behav;