#ifndef  __SYSTEM_DEFINED
#define __SYSTEM_DEFINED

//--------------------------------------------------------------------------//
// Header files																//
//--------------------------------------------------------------------------//
#include <defBF533.h>
#include <cdefBF533.h>
#include <sys\exception.h>
#include <ccblkfn.h>
#include <sysreg.h>

#include "types.h"
#include "globvar.h"



#define 	XDIM 	352
#define 	YDIM	288

#define ADV7181_IDENT_W	0x40
#define ADV7181_IDENT_R	0x41

#define IDLE		0
#define BUSY		1
#define DONE		2


#define VIDEOBUFFER1	1
#define VIDEOBUFFER2	2


#define BF533_EZKIT	0
#define BF533_EVM	1

#define USE_MEM_DMA	0

#define SCLK	81000000


//--------------------------------------------------------------------------//
// Symbolic constants															//
//--------------------------------------------------------------------------//
// addresses for CPLD
#define pLED  				(volatile unsigned char *)0x203C0000
#define p7Section 			(volatile unsigned char *)0x203C4000
#define pCtrlSetReg1			(volatile unsigned char *)0x203C8000
#define pCtrlSetReg2			(volatile unsigned char *)0x203CC000
#define pSL811BaseAddr		(volatile unsigned char *)0x203D8000
#define pLcdBaseAddr		(volatile unsigned char *)0x203DC000
#define pCtrlClrReg1			(volatile unsigned char *)0x203F8000
#define pCtrlClrReg2			(volatile unsigned char *)0x203FC000


#define pIDECS0BaseAddr		(volatile unsigned short *)0x203E0000
#define pIDECS1BaseAddr		(volatile unsigned short *)0x203E4000
#define pNAND_CtrlBaseaAddr	(volatile unsigned char *)0x203E8000
#define pNAND_BaseaAddr	(volatile unsigned char *)0x203EC000
#define pSPI_CtrlBaseaAddr	(volatile unsigned char *)0x203F0000

// Bits definition Control register in CPLD
#define CTRL_ADV7181_RESET		0x01 // Active Low
#define CTRL_PPI_PF_ACTIVE		0x02 // Active High
#define CTRL_ADV7171_RESET		0x04 // Active Low
#define CTRL_ISP1582_RESET		0x08 // Active Low
#define CTRL_OV6650_OUTPUT		0x10 // Active High
#define CTRL_OV6650_RESET		0x20 // Active High
#define CTRL_CS8900_RESET		0x40 // Active High

// Bits definition SPI control register in CPLD
#define  SPI_CTRL_NONE		0x07
#define  SPI_CTRL_MCP2515	0x00
#define  SPI_CTRL_MMC		0x01
#define  SPI_CTRL_AIC23B	0x02
#define  SPI_CTRL_TSC2200	0x03

// The video frame buffer base address
#define VIDEO_FRAME_BUFFER_BASE		0x01000000
// The LCD frame buffer 0 base address
#define LCD_FRAME_BUFFER_0_BASE		0x01108000
// The LCD DMA descriptor base address
#define LCD_DMA_DESCRIPTOR_BASE		0x01147000
// The audio buffer base address
#define AUDIO_BUFFER_BASE				0x01148000
// The audio DMA descriptor base address
#define AUDIO_DMA_DESCRIPTOR_BASE	0x0114C000
// The SDRAM Disk base address
#define RAM_DISK_BASE					0x011C0000
// The LCD frame buffer 1 base address
#define LCD_FRAME_BUFFER_1_BASE		0x019C0000
//--------------------------------------------------------------------------//
// Prototypes																	//
//--------------------------------------------------------------------------//
// in file Initialization.c

#endif