#include <cDefBF561.h>
#include <sysreg.h>
#include <ccblkfn.h>
#include <sys\exception.h>
#include <signal.h>

#define CLKIN	  (30.0e6)		// clockin frequency in Hz
#define CORECLK  (600.0e6)		// core clock frequency in Hz
#define SYSCLK	 (120.0e6)		// system clock frequency in Hz

//function define
void Init_EBIU(void);
void Init_SDRAM(void);
void Init_SPORTS1(void);
void Init_Interrupts_for_FPGA_init(void);
void Init_FPGA(void);
void Init_PF(void);
void Init_SPORTS0(void);
void START_SPORT0_RX(void);
void Init_Interrupts_for_SPORT0(void);
void Set_PLL(short CoreCLOCK_multiplier, short SCLK_divider);
void delay(void);


EX_INTERRUPT_HANDLER(SPORT1_TX_ISR_For_FPGA_Init);
EX_INTERRUPT_HANDLER(PF_Interrupt_ISR);
EX_INTERRUPT_HANDLER(SPORT1_RX_ISR_For_Recieve_Data);
EX_INTERRUPT_HANDLER(SPORT0_RX_ISR_For_Command_Down_Load);
EX_INTERRUPT_HANDLER(SPORT0_RX_ISR_For_Data_Down_Load);
EX_INTERRUPT_HANDLER(SPORT0_TX_ISR_For_Data_Up_Load);

//Variable define
extern char FPGA_Parameter[30];
//extern char Data_Buffer[2600];
extern volatile char Data_Buffer[2600];
extern char channel1[512];			    	//front 37degree data buffer
extern char channel2[512];			    	//back 37degree data buffer
extern char channel3[512];					//0degree data buffer
extern char channel4[512];					//front 70degree data buffer
extern char channel5[512];					//back 70degree data buffer

extern char FPGA_Config_Done;
extern char Dummy_TX_Done;
extern char Dummy_RX_Done;

extern short Command_Address;
extern char DSP_Config_Done;