#include "FPGA_Test.h"

EX_INTERRUPT_HANDLER(SPORT0_RX_ISR_For_Command_Down_Load)
{
	//disable SPORT0 RX
	*pSPORT0_RCR1 = *pSPORT0_RCR1 &0xfffe;
	ssync();
	*pDMA2_0_IRQ_STATUS  = 0x0001;
	ssync();
	*pDMA2_0_CONFIG	= *pDMA2_0_CONFIG & 0xfffe ;
	ssync();
	
	if(Command_Address == 0xa1c2)      //Xscal --> DSP
	{
		//re_config SPORT0 RX DMA
		*pDMA2_0_START_ADDR = FPGA_Parameter;
		ssync();
		*pDMA2_0_X_COUNT = 15;
		ssync();
		
		//re_config interrupt
		register_handler(ik_ivg8, SPORT0_RX_ISR_For_Data_Down_Load);
		
		*pDMA2_0_IRQ_STATUS  = 0x0001;
		ssync();
		*pDMA2_0_CONFIG	= *pDMA2_0_CONFIG | 0x0001 ;
		ssync();
		*pSPORT0_RCR1 = *pSPORT0_RCR1 | 0x0001;
		ssync();
		
		//set PF8
		*pFIO0_FLAG_S = 0x0100;
		ssync();
		
	}
	else if(Command_Address == 0xb0d3)  //Xscal <-- DSP
	{

		//start SPORT0_TX
		*pDMA2_1_IRQ_STATUS  = 0x0001;
		ssync();
		*pDMA2_1_CONFIG	= *pDMA2_1_CONFIG | 0x0001 ;
		ssync();
		*pSPORT0_TCR1 = *pSPORT0_TCR1 | 0x0001;
		ssync();
		
		//set PF8
		*pFIO0_FLAG_S = 0x0100;
		ssync();
	}
	else								//error
	{
		*pFIO0_FLAG_C = 0x0100;
		ssync();
		
		//restart SPORT0_RX
		*pDMA2_0_IRQ_STATUS  = 0x0001;
		ssync();
		*pDMA2_0_CONFIG	= *pDMA2_0_CONFIG | 0x0001;
		ssync();
		*pSPORT0_RCR1 = *pSPORT0_RCR1 | 0x0001;
		ssync();
	}
}

EX_INTERRUPT_HANDLER(SPORT0_RX_ISR_For_Data_Down_Load)
{
	*pSPORT0_RCR1 = *pSPORT0_RCR1 & 0xfffe;
	ssync();
	*pDMA2_0_IRQ_STATUS  = 0x0001;
	ssync();
	*pDMA2_0_CONFIG	= *pDMA2_0_CONFIG & 0xfffe;
	ssync();
	
	register_handler(ik_ivg8, SPORT0_RX_ISR_For_Command_Down_Load);
	*pDMA2_0_IRQ_STATUS  = 0x0001;
	ssync();
	*pDMA2_0_CONFIG	= *pDMA2_0_CONFIG | 0x0001;
	ssync();
	*pSPORT0_RCR1 = *pSPORT0_RCR1 | 0x0001;
	ssync();
	
	DSP_Config_Done = 1;
	
	//clear PF8
	*pFIO0_FLAG_C = 0x0100;
	ssync();
}

EX_INTERRUPT_HANDLER(SPORT0_TX_ISR_For_Data_Up_Load)
{
	*pSPORT0_TCR1 = *pSPORT0_TCR1 & 0xfffe;
	ssync();
	*pDMA2_1_IRQ_STATUS  = 0x0001;
	ssync();
	*pDMA2_1_CONFIG	= *pDMA2_1_CONFIG & 0xfffe;
	ssync();
	
	register_handler(ik_ivg8, SPORT0_RX_ISR_For_Command_Down_Load);
	*pDMA2_0_IRQ_STATUS  = 0x0001;
	ssync();
	*pDMA2_0_CONFIG	= *pDMA2_0_CONFIG | 0x0001;
	ssync();
	*pSPORT0_RCR1 = *pSPORT0_RCR1 | 0x0001;
	ssync();
	
	//clear PF8
	*pFIO0_FLAG_C = 0x0100;
	ssync();	
}