#include "FPGA_Test.h"

//SPORT0 Setup
void Init_SPORTS0(void)
{
	//MSB first External TCLK/RCLK External FRAME
	// configure SPORT0 receiver and transmitter 16-bit transfer
	*pSPORT0_RCR1 		= 0x0400;
	ssync();	
	*pSPORT0_RCR2 		= 0x000f;				
	ssync();	
	*pSPORT0_TCR1		= 0x0400;
	ssync();	
	*pSPORT0_TCR2		= 0x000f;

	//configure SPORT0 TX DMA   stop mode generate interrupt memory read 16-bit
	*pDMA2_1_CONFIG = 0x00a4;
	ssync();
	*pDMA2_1_START_ADDR = Data_Buffer;
	ssync();
	*pDMA2_1_X_COUNT = 1300;
	ssync();
	*pDMA2_1_X_MODIFY = 2;
	ssync();
	*pDMA2_1_PERIPHERAL_MAP   = 0x1000;
	ssync();
	//configure SPORT1 RX DMA	stop mode generate interrupt memory write 16-bit
	*pDMA2_0_CONFIG = 0x00a6;
	ssync();
	*pDMA2_0_START_ADDR = Command_Address;
	ssync();
	*pDMA2_0_X_COUNT = 1;
	ssync();
	*pDMA2_0_X_MODIFY = 2;
	ssync();
	*pDMA2_0_PERIPHERAL_MAP   = 0x0000;
	ssync();
}

//--------------------------------------------------------------------------//
// Function:	Init_Interrupts_for_SPORT0											//
//																			//
// Parameters:	None														//
//																			//
// Return:		None														//
//																			//
// Description:	Configure SPORT0 TX and RX interrupts.						//
//--------------------------------------------------------------------------//
void Init_Interrupts_for_SPORT0(void)
{
	// configure interrupts
	// SPORT0 RX = ID 1; SPORT0 TX = ID 2

	*pSICB_IAR2 = 0x1fffffff;
	*pSICB_IAR3 = 0xfffffff2;

	// assign SPORT0 TX ISR to interrupt vector 9
	register_handler(ik_ivg9, SPORT0_TX_ISR_For_Data_Up_Load);	
	// assign SPORT1 RX ISR to interrupt vector 8
	register_handler(ik_ivg8, SPORT0_RX_ISR_For_Command_Down_Load);	

	// enable SPORT0 RX interrupt
	*pSICB_IMASK0 = *pSICB_IMASK0 | 0x01800000;					

}

void Start_SPORT0_RX(void)
{
	*pDMA2_0_IRQ_STATUS  = 0x0001;
	ssync();
	*pDMA2_0_CONFIG	= *pDMA2_0_CONFIG | 0x0001;
	ssync();
	*pSPORT0_RCR1 = *pSPORT0_RCR1 | 0x0001;
	ssync();
	delay();
	
	//set PF8
	*pFIO0_FLAG_S = 0x0100;
	ssync();
}