# Generated by the VisualDSP++ IDDE

# Note:  Any changes made to this Makefile will be lost the next time the
# matching project file is loaded into the IDDE.  If you wish to preserve
# changes, rename this file and run it externally to the IDDE.

# The syntax of this Makefile is such that GNU Make v3.77 or higher is
# required.

# The current working directory should be the directory in which this
# Makefile resides.

# Supported targets:
#     UART_Debug
#     UART_Debug_clean

# Define this variable if you wish to run this Makefile on a host
# other than the host that created it and VisualDSP++ may be installed
# in a different directory.

ADI_DSP=E:\Program Files\Analog Devices\VisualDSP 3.5 16-Bit

ifndef ADI_DSP_MAKE
ADI_DSP_MAKE=E:/Program\ Files/Analog\ Devices/VisualDSP\ 3.5\ 16-Bit
endif

# $VDSP is a gmake-friendly version of ADI_DIR

empty:=
space:= $(empty) $(empty)
VDSP_INTERMEDIATE=$(subst \,/,$(ADI_DSP))
VDSP=$(subst $(space),\$(space),$(VDSP_INTERMEDIATE))

# Define the command to use to delete files (which is different on Win95/98
# and Windows NT/2000)

ifeq ($(OS),Windows_NT)
RM=cmd /C del /F /Q
else
RM=command /C del
endif

#
# Begin "UART_Debug" configuration
#

ifeq ($(MAKECMDGOALS),UART_Debug)

UART_Debug : ./Debug/sml2.sm ./Debug/p0.dxe ./Debug/p1.dxe 

./Debug/dummy.doj :./dummy.c 
	$(VDSP)/ccblkfn.exe -c .\dummy.c -g -proc ADSP-BF561 -o .\Debug\dummy.doj -MM

./Debug/sml2.sm ./Debug/p0.dxe ./Debug/p1.dxe :./FPGA_TEST.ldf ./Debug/dummy.doj ./sml2.dlb $(VDSP)/Blackfin/lib/libsmall532.dlb $(VDSP)/Blackfin/lib/__initsbsz532.doj $(VDSP)/Blackfin/lib/libc532.dlb $(VDSP)/Blackfin/lib/libm3free532.dlb $(VDSP)/Blackfin/lib/libevent532.dlb $(VDSP)/Blackfin/lib/libx561.dlb $(VDSP)/Blackfin/lib/libio561.dlb $(VDSP)/Blackfin/lib/libcpp532.dlb $(VDSP)/Blackfin/lib/libcpprt532.dlb $(VDSP)/Blackfin/lib/libdsp532.dlb $(VDSP)/Blackfin/lib/libsftflt532.dlb $(VDSP)/Blackfin/lib/libetsi532.dlb $(VDSP)/Blackfin/lib/idle532.doj $(VDSP)/Blackfin/lib/librt_fileio532.dlb ./sml3.dlb $(VDSP)/Blackfin/lib/crtsf561.doj $(VDSP)/Blackfin/lib/cplbtab561a.doj ./corea.dlb $(VDSP)/Blackfin/lib/cplbtab561b.doj ./coreb.dlb 
	$(VDSP)/ccblkfn.exe .\Debug\dummy.doj -T .\FPGA_TEST.ldf -L .\Debug -flags-link -od,.\Debug -o .\Debug\UART.dxe -proc ADSP-BF561 -flags-link -MM

endif

ifeq ($(MAKECMDGOALS),UART_Debug_clean)

UART_Debug_clean:
	$(RM) ".\Debug\dummy.doj"
	$(RM) ".\Debug\sml2.sm"
	$(RM) ".\Debug\p0.dxe"
	$(RM) ".\Debug\p1.dxe"
	$(RM) ".\Debug\*.ipa"
	$(RM) ".\Debug\*.opa"
	$(RM) ".\Debug\*.ti"

endif