?? fpga_test.ldf
字號:
INPUT_SECTIONS( $LIBRARIES_SML3(voldata))
} >MEM_SDRAM0
sdram0_bsz ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($LIBRARIES_SML3(bsz))
} >MEM_SDRAM0
bsz_init
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS(bsz_init))
INPUT_SECTIONS( $LIBRARIES_SML2(bsz_init))
INPUT_SECTIONS( $LIBRARIES_SML3(bsz_init))
} >MEM_SDRAM0
.meminit {} >MEM_SDRAM0
#if defined(__ADI_MULTICORE)
heap
{
// Allocate a heap for the application
ldf_heap_space = .;
ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(MEM_SDRAM0_HEAP) - 1;
ldf_heap_length = ldf_heap_end - ldf_heap_space;
} >MEM_SDRAM0_HEAP
#endif
}
}
/* Core A */
PROCESSOR p0
{
MEMORY
{
/* ----- Core A ----- */
MEM_A_L1_SCRATCH { /* L1 Scratchpad - 4K */
TYPE(RAM) WIDTH(8)
START(0xFFB00000) END(0xFFB00FFF)
}
MEM_A_L1_CODE_CACHE { /* Instruction SRAM/Cache - 16K */
TYPE(RAM) WIDTH(8)
START(0xFFA10000) END(0xFFA13FFF)
}
MEM_A_L1_CODE { /* Instruction SRAM - 16K */
TYPE(RAM) WIDTH(8)
START(0xFFA00000) END(0xFFA03FFF)
}
#ifdef USE_CACHE /* { */
MEM_A_L1_DATA_B_CACHE { /* Data Bank B SRAM/Cache - 16K */
TYPE(RAM) WIDTH(8)
START(0xFF904000) END(0xFF907FFF)
}
MEM_A_L1_DATA_B { /* Data Bank B SRAM - 12K of 16K */
TYPE(RAM) WIDTH(8)
START(0xFF901000) END(0xFF903FFF)
}
#else /* } { USE_CACHE */
MEM_A_L1_DATA_B { /* Data Bank B SRAM - 28K of 32K */
TYPE(RAM) WIDTH(8)
START(0xFF901000) END(0xFF907FFF)
}
#endif /* } USE_CACHE */
MEM_A_L1_STACK { /* Data Bank B SRAM - 4K of 16K */
TYPE(RAM) WIDTH(8)
START(0xFF900000) END(0xFF900FFF)
}
#ifdef USE_CACHE /* { */
MEM_A_L1_DATA_A_CACHE { /* Data Bank A SRAM/Cache - 16K */
TYPE(RAM) WIDTH(8)
START(0xFF804000) END(0xFF807FFF)
}
MEM_A_L1_DATA_A { /* Data Bank A SRAM - 16K */
TYPE(RAM) WIDTH(8)
START(0xFF800000) END(0xFF803FFF)
}
#else /* } { USE_CACHE */
MEM_A_L1_DATA_A { /* Data Bank A SRAM - 16K */
TYPE(RAM) WIDTH(8)
START(0xFF800000) END(0xFF807FFF)
}
#endif /* } USE_CACHE */
}
OUTPUT( $COMMAND_LINE_OUTPUT_DIRECTORY/p0.dxe )
/* Following address must match start of MEM_A_L1_CODE */
RESOLVE(start,0xFFA00000)
KEEP(start,_main)
LINK_AGAINST($COMMAND_LINE_OUTPUT_DIRECTORY/sml2.sm)
SECTIONS
{
program_ram
{
INPUT_SECTION_ALIGN(4)
__CORE = 0;
INPUT_SECTIONS( $OBJECTS_CORE_A(L1_code) $LIBRARIES_CORE_A(L1_code))
INPUT_SECTIONS( $OBJECTS_CORE_A(cplb) $LIBRARIES_CORE_A(cplb))
INPUT_SECTIONS( $OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))
INPUT_SECTIONS( $OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))
INPUT_SECTIONS( $OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
} >MEM_A_L1_CODE
l1_code
{
#ifdef USE_CACHE /* { */
___l1_code_cache = 1;
#else
___l1_code_cache = 0;
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS_CORE_A(L1_code) $LIBRARIES_CORE_A(L1_code))
INPUT_SECTIONS( $OBJECTS_CORE_A(cplb) $LIBRARIES_CORE_A(cplb))
INPUT_SECTIONS( $OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))
INPUT_SECTIONS( $OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
#endif /* USE_CACHE } */
} >MEM_A_L1_CODE_CACHE
bsz_init
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS_CORE_A(bsz_init) $LIBRARIES_CORE_A(bsz_init))
} >MEM_A_L1_DATA_A
.meminit{} >MEM_A_L1_DATA_A
data
{
INPUT_SECTION_ALIGN(4)
#ifndef USE_CACHE /* { */
___l1_data_cache_a = 0;
#endif /* } USE_CACHE */
INPUT_SECTIONS( $OBJECTS_CORE_A(L1_data_a) $LIBRARIES_CORE_A(L1_data_a))
INPUT_SECTIONS( $OBJECTS_CORE_A(cplb_data) $LIBRARIES_CORE_A(cplb_data))
INPUT_SECTIONS($OBJECTS_CORE_A(data1) $LIBRARIES_CORE_A(data1))
INPUT_SECTIONS($OBJECTS_CORE_A(voldata) $LIBRARIES_CORE_A(voldata))
#ifdef __cplusplus /* { */
INPUT_SECTIONS( $OBJECTS_CORE_A(.edt) $LIBRARIES_CORE_A(.edt) )
INPUT_SECTIONS( $OBJECTS_CORE_A(.cht) $LIBRARIES_CORE_A(.cht) )
#endif /* } */
} >MEM_A_L1_DATA_A
constdata
{
INPUT_SECTION_ALIGN(4)
#ifndef USE_CACHE /* { */
___l1_data_cache_b = 0;
#endif /* } USE_CACHE */
INPUT_SECTIONS( $OBJECTS_CORE_A(L1_data_b) $LIBRARIES_CORE_A(L1_data_b))
INPUT_SECTIONS($OBJECTS_CORE_A(constdata) $LIBRARIES_CORE_A(constdata))
#ifdef __cplusplus /* { */
INPUT_SECTIONS( $OBJECTS_CORE_A(ctor) $LIBRARIES_CORE_A(ctor) )
INPUT_SECTIONS( $OBJECTS_CORE_A(ctorl) $LIBRARIES_CORE_A(ctorl) )
INPUT_SECTIONS( $OBJECTS_CORE_A(.gdt) $LIBRARIES_CORE_A(.gdt) )
INPUT_SECTIONS( $OBJECTS_CORE_A(.gdtl) $LIBRARIES_CORE_A(.gdtl) )
INPUT_SECTIONS( $OBJECTS_CORE_A(.frt) $LIBRARIES_CORE_A(.frt) )
INPUT_SECTIONS( $OBJECTS_CORE_A(.frtl) $LIBRARIES_CORE_A(.frtl) )
INPUT_SECTIONS( $OBJECTS_CORE_A(.edt) $LIBRARIES_CORE_A(.edt) )
INPUT_SECTIONS( $OBJECTS_CORE_A(.cht) $LIBRARIES_CORE_A(.cht) )
#endif /* } */
} >MEM_A_L1_DATA_B
#ifdef USE_CACHE /* { */
l1_data_a
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_a = 1;
} >MEM_A_L1_DATA_A_CACHE
l1_data_b
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_b = 1;
} >MEM_A_L1_DATA_B_CACHE
#endif /* USE_CACHE } */
bsz_L1_data_a ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS_CORE_A(bsz) $LIBRARIES_CORE_A(bsz))
} >MEM_A_L1_DATA_A
bsz_L1_data_b ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS_CORE_A(bsz) $LIBRARIES_CORE_A(bsz))
} >MEM_A_L1_DATA_B
stack
{
ldf_stack_space = .;
ldf_stack_end = ldf_stack_space + MEMORY_SIZEOF(MEM_A_L1_STACK);
} >MEM_A_L1_STACK
#if !defined(__ADI_MULTICORE)
heap
{
// Allocate a heap for the application
ldf_heap_space = .;
ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(MEM_SDRAM0_HEAP_A) - 1;
ldf_heap_length = ldf_heap_end - ldf_heap_space;
} >MEM_SDRAM0_HEAP_A
#endif
}
}
/* Core B */
PROCESSOR p1
{
MEMORY {
/* ----- Core B ----- */
MEM_B_L1_SCRATCH { /* L1 Scratchpad - 4K */
TYPE(RAM) WIDTH(8)
START(0xFF700000) END(0xFF700FFF)
}
MEM_B_L1_CODE_CACHE { /* L1 Instruction SRAM/Cache - 16K */
TYPE(RAM) WIDTH(8)
START(0xFF610000) END(0xFF613FFF)
}
MEM_B_L1_CODE { /* L1 Instruction SRAM - 16K */
TYPE(RAM) WIDTH(8)
START(0xFF600000) END(0xFF603FFF)
}
#ifdef USE_CACHE /* { */
MEM_B_L1_DATA_B_CACHE { /* L1 Data Bank B SRAM/Cache - 16K */
TYPE(RAM) WIDTH(8)
START(0xFF504000) END(0xFF507FFF)
}
MEM_B_L1_DATA_B { /* L1 Data Bank B SRAM - 12K of 16K */
TYPE(RAM) WIDTH(8)
START(0xFF501000) END(0xFF503FFF)
}
#else /* } { USE_CACHE */
MEM_B_L1_DATA_B { /* L1 Data Bank B SRAM - 28K of 32K */
TYPE(RAM) WIDTH(8)
START(0xFF501000) END(0xFF507FFF)
}
#endif /* } USE_CACHE */
MEM_B_L1_STACK { /* L1 Data Bank B SRAM - 4K of 16K */
TYPE(RAM) WIDTH(8)
START(0xFF500000) END(0xFF500FFF)
}
#ifdef USE_CACHE /* { */
MEM_B_L1_DATA_A_CACHE { /* L1 Data Bank A SRAM/Cache - 16K */
TYPE(RAM) WIDTH(8)
START(0xFF404000) END(0xFF407FFF)
}
MEM_B_L1_DATA_A { /* L1 Data Bank A SRAM - 16K */
TYPE(RAM) WIDTH(8)
START(0xFF401000) END(0xFF403FFF)
}
#else /* } { USE_CACHE */
MEM_B_L1_DATA_A { /* L1 Data Bank A SRAM - 32K */
TYPE(RAM) WIDTH(8)
START(0xFF400000) END(0xFF407FFF)
}
#endif /* } USE_CACHE */
}
OUTPUT( $COMMAND_LINE_OUTPUT_DIRECTORY/p1.dxe )
/* Following address must match start of MEM_B_L1_PROGRAM */
RESOLVE(start,0xFF600000)
KEEP(start,_main)
LINK_AGAINST($COMMAND_LINE_OUTPUT_DIRECTORY/sml2.sm)
SECTIONS
{
program_ram
{
INPUT_SECTION_ALIGN(4)
__CORE = 1;
INPUT_SECTIONS( $OBJECTS_CORE_B(L1_code) $LIBRARIES_CORE_B(L1_code))
INPUT_SECTIONS( $OBJECTS_CORE_B(cplb) $LIBRARIES_CORE_B(cplb))
INPUT_SECTIONS( $OBJECTS_CORE_B(cplb_code) $LIBRARIES_CORE_B(cplb_code))
INPUT_SECTIONS( $OBJECTS_CORE_B(noncache_code) $LIBRARIES_CORE_B(noncache_code))
INPUT_SECTIONS( $OBJECTS_CORE_B(program) $LIBRARIES_CORE_B(program))
} >MEM_B_L1_CODE
l1_code
{
INPUT_SECTION_ALIGN(4)
#ifdef USE_CACHE /* { */
___l1_code_cache = 1;
#else
___l1_code_cache = 0;
INPUT_SECTIONS( $OBJECTS_CORE_B(L1_code) $LIBRARIES_CORE_B(L1_code))
INPUT_SECTIONS( $OBJECTS_CORE_B(cplb_code) $LIBRARIES_CORE_B(cplb_code))
INPUT_SECTIONS( $OBJECTS_CORE_B(cplb) $LIBRARIES_CORE_B(cplb))
INPUT_SECTIONS( $OBJECTS_CORE_B(program) $LIBRARIES_CORE_B(program))
#endif /* USE_CACHE } */
} >MEM_B_L1_CODE_CACHE
bsz_init
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS_CORE_B(bsz_init) $LIBRARIES_CORE_B(bsz_init))
} >MEM_B_L1_DATA_A
.meminit{} >MEM_B_L1_DATA_A
constdata_L1_data_a
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJECTS_CORE_B(constdata) $LIBRARIES_CORE_B(constdata))
} >MEM_B_L1_DATA_B
data_L1_data_a
{
INPUT_SECTION_ALIGN(4)
#ifndef USE_CACHE /* { */
___l1_data_cache_a = 0;
#endif /* } USE_CACHE */
INPUT_SECTIONS( $OBJECTS_CORE_B(L1_data_a) $LIBRARIES_CORE_B(L1_data_a))
INPUT_SECTIONS( $OBJECTS_CORE_B(cplb_data) $LIBRARIES_CORE_B(cplb_data))
INPUT_SECTIONS($OBJECTS_CORE_B(data1) $LIBRARIES_CORE_B(data1))
INPUT_SECTIONS($OBJECTS_CORE_B(voldata) $LIBRARIES_CORE_B(voldata))
#ifdef __cplusplus /* { */
INPUT_SECTIONS( $OBJECTS_CORE_B(.edt) $LIBRARIES_CORE_B(.edt) )
INPUT_SECTIONS( $OBJECTS_CORE_B(.cht) $LIBRARIES_CORE_B(.cht) )
#endif /* } */
} >MEM_B_L1_DATA_A
constdata_L1_data_b
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS_CORE_B(L1_data_b) $LIBRARIES_CORE_B(L1_data_b))
INPUT_SECTIONS($OBJECTS_CORE_B(constdata) $LIBRARIES_CORE_B(constdata))
#ifdef __cplusplus /* { */
INPUT_SECTIONS( $OBJECTS_CORE_B(ctor) $LIBRARIES_CORE_B(ctor) )
INPUT_SECTIONS( $OBJECTS_CORE_B(ctorl) $LIBRARIES_CORE_B(ctorl) )
INPUT_SECTIONS( $OBJECTS_CORE_B(.gdt) $LIBRARIES_CORE_B(.gdt) )
INPUT_SECTIONS( $OBJECTS_CORE_B(.gdtl) $LIBRARIES_CORE_B(.gdtl) )
INPUT_SECTIONS( $OBJECTS_CORE_B(.frt) $LIBRARIES_CORE_B(.frt) )
INPUT_SECTIONS( $OBJECTS_CORE_B(.frtl) $LIBRARIES_CORE_B(.frtl) )
INPUT_SECTIONS( $OBJECTS_CORE_B(.edt) $LIBRARIES_CORE_B(.edt) )
INPUT_SECTIONS( $OBJECTS_CORE_B(.cht) $LIBRARIES_CORE_B(.cht) )
#endif /* } */
} >MEM_B_L1_DATA_B
data_L1_data_b
{
INPUT_SECTION_ALIGN(4)
#ifndef USE_CACHE /* { */
___l1_data_cache_b = 0;
#endif /* } USE_CACHE */
INPUT_SECTIONS( $OBJECTS_CORE_B(L1_data_a) $LIBRARIES_CORE_B(L1_data_a))
INPUT_SECTIONS( $OBJECTS_CORE_B(cplb_data) $LIBRARIES_CORE_B(cplb_data))
INPUT_SECTIONS($OBJECTS_CORE_B(data1) $LIBRARIES_CORE_B(data1))
INPUT_SECTIONS($OBJECTS_CORE_B(voldata) $LIBRARIES_CORE_B(voldata))
} >MEM_B_L1_DATA_B
#ifdef USE_CACHE /* { */
l1_data_a
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_a = 1;
} >MEM_B_L1_DATA_A_CACHE
l1_data_b
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_b = 1;
} >MEM_B_L1_DATA_B_CACHE
#endif /* } USE_CACHE */
bsz_L1_data_a ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS_CORE_B(bsz) $LIBRARIES_CORE_B(bsz))
} >MEM_B_L1_DATA_A
bsz_L1_data_b ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS_CORE_B(bsz) $LIBRARIES_CORE_B(bsz))
} >MEM_B_L1_DATA_B
stack
{
ldf_stack_space = .;
ldf_stack_end = ldf_stack_space + MEMORY_SIZEOF(MEM_B_L1_STACK);
} >MEM_B_L1_STACK
#if !defined(__ADI_MULTICORE)
heap
{
// Allocate a heap for the application
ldf_heap_space = .;
ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(MEM_SDRAM0_HEAP_B) - 1;
ldf_heap_length = ldf_heap_end - ldf_heap_space;
} >MEM_SDRAM0_HEAP_B
#endif
}
}
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