#ifndef  __ISP1161_DEFINED
#define __ISP1161_DEFINED

#include <cDefBF561.h>
#include <sysreg.h>
#include <ccblkfn.h>
#include <sys\exception.h>
#include <signal.h>

extern void Set_PLL(short CoreCLOCK_multiplier, short SCLK_divider);

#define CLKIN	  (27.0e6)		// clockin frequency in Hz
#define CORECLK  (540.0e6)		// core clock frequency in Hz
#define SYSCLK	 (90.0e6)		// system clock frequency in Hz
// ISP1161 base address
#define ISP1161_Base	0x2D800000


#define pISP1161_Base				((volatile unsigned short *)ISP1161_Base)
#define pCtrlSetReg1					(volatile unsigned char *)0x2C800000

#define pISP1161_HC_DATA			((volatile unsigned short *)(ISP1161_Base + (0x00 << 1)))
#define pISP1161_HC_CMD			((volatile unsigned short *)(ISP1161_Base + (0x01 << 1)))
#define pISP1161_DC_DATA			((volatile unsigned short *)(ISP1161_Base + (0x02 << 1)))
#define pISP1161_DC_CMD			((volatile unsigned short *)(ISP1161_Base + (0x03 << 1)))


// Command codes
#define READ_CHIP_ID		0x0027

#define READ_SCRATCH		0x0028
#define WRITE_SCRATCH		0x00A8


// Chip ID register definition
#define ISP1161_CHIP_ID		0x6123


#endif