?? mk30dz10.h
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/*
** ###################################################################
** Processors: MK30DN512ZVLK10
** MK30DN512ZVLL10
** MK30DN512ZVLQ10
** MK30DX128ZVLQ10
** MK30DX256ZVLQ10
** MK30DN512ZVMB10
** MK30DN512ZVMC10
** MK30DN512ZVMD10
** MK30DX256ZVMD10
** MK30DX128ZVMD10
**
** Compilers: Freescale C/C++ for Embedded ARM
** GNU ARM C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K30P144M100SF2RM, Rev. 5, 8 May 2011
** Version: rev. 1.1, 2011-06-15
**
** Abstract:
** This header file implements peripheral memory map for MK30DZ10
** processor.
**
** Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2011-03-30)
** Initial version.
** Changes with respect to the previous MK10NxxVMD100 header file:
** RTC - CCR register removed. Replaced by IER register.
** CRC - added CTRLHU register for 8-bit access to the CTRL register.
** FB - bit FB_CSCR_EXALE renamed to FB_CSCR_EXTS.
** SIM- bit group FSIZE in SIM_FCFG1 split into groups PFSIZE and NVMSIZE.
** Added registers for core modules - CoreDebug, DWT, ETB, ETF, ETM, FPB, ITM, TPIU.
** - rev. 1.1 (2011-06-15)
** Registers updated according to the new reference manual revision - Rev. 5, 8 May 2011
** I2S - bit SSIEN in I2S_CR register renamed to I2SEN.
** SDHC - bit VOLTSEL in SDHC_VENDOR register removed.
** TSI - registers TSI_CNTR1 to TSI_CNTR15, bit group CNTN renamed to CTN1, bit group CNTN1 renamed to CTN.
**
** ###################################################################
*/
/**
* @file MK30DZ10.h
* @version 1.1
* @date 2011-06-15
* @brief Peripheral memory map for MK30DZ10
*
* This header file implements peripheral memory map for MK30DZ10 processor.
*/
/* ----------------------------------------------------------------------------
-- MCU activation
---------------------------------------------------------------------------- */
/* Prevention from multiple including the same memory map */
#if !defined(MCU_MK30DZ10) /* Check if memory map has not been already included */
#define MCU_MK30DZ10
/* Check if another memory map has not been also included */
#if (defined(MCU_ACTIVE))
#error MK30DZ10 memory map: There is already included another memory map. Only one memory map can be included.
#endif /* (defined(MCU_ACTIVE)) */
#define MCU_ACTIVE
#include <stdint.h>
/** Memory map version 1.1 */
#define MCU_MEM_MAP_VERSION 0x0101u
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/**
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
typedef enum {
INT_Initial_Stack_Pointer = 0, /**< Initial stack pointer */
INT_Initial_Program_Counter = 1, /**< Initial program counter */
INT_NMI = 2, /**< Non-maskable interrupt */
INT_Hard_Fault = 3, /**< Hard fault exception */
INT_Mem_Manage_Fault = 4, /**< Memory Manage Fault */
INT_Bus_Fault = 5, /**< Bus fault exception */
INT_Usage_Fault = 6, /**< Usage fault exception */
INT_Reserved7 = 7, /**< Reserved interrupt 7 */
INT_Reserved8 = 8, /**< Reserved interrupt 8 */
INT_Reserved9 = 9, /**< Reserved interrupt 9 */
INT_Reserved10 = 10, /**< Reserved interrupt 10 */
INT_SVCall = 11, /**< A supervisor call exception */
INT_DebugMonitor = 12, /**< Debug Monitor */
INT_Reserved13 = 13, /**< Reserved interrupt 13 */
INT_PendableSrvReq = 14, /**< PendSV exception - request for system level service */
INT_SysTick = 15, /**< SysTick Interrupt */
INT_DMA0 = 16, /**< DMA Channel 0 Transfer Complete */
INT_DMA1 = 17, /**< DMA Channel 1 Transfer Complete */
INT_DMA2 = 18, /**< DMA Channel 2 Transfer Complete */
INT_DMA3 = 19, /**< DMA Channel 3 Transfer Complete */
INT_DMA4 = 20, /**< DMA Channel 4 Transfer Complete */
INT_DMA5 = 21, /**< DMA Channel 5 Transfer Complete */
INT_DMA6 = 22, /**< DMA Channel 6 Transfer Complete */
INT_DMA7 = 23, /**< DMA Channel 7 Transfer Complete */
INT_DMA8 = 24, /**< DMA Channel 8 Transfer Complete */
INT_DMA9 = 25, /**< DMA Channel 9 Transfer Complete */
INT_DMA10 = 26, /**< DMA Channel 10 Transfer Complete */
INT_DMA11 = 27, /**< DMA Channel 11 Transfer Complete */
INT_DMA12 = 28, /**< DMA Channel 12 Transfer Complete */
INT_DMA13 = 29, /**< DMA Channel 13 Transfer Complete */
INT_DMA14 = 30, /**< DMA Channel 14 Transfer Complete */
INT_DMA15 = 31, /**< DMA Channel 15 Transfer Complete */
INT_DMA_Error = 32, /**< DMA Error Interrupt */
INT_MCM = 33, /**< Normal Interrupt */
INT_FTFL = 34, /**< FTFL Interrupt */
INT_Read_Collision = 35, /**< Read Collision Interrupt */
INT_LVD_LVW = 36, /**< Low Voltage Detect, Low Voltage Warning */
INT_LLW = 37, /**< Low Leakage Wakeup */
INT_Watchdog = 38, /**< WDOG Interrupt */
INT_Reserved39 = 39, /**< Reserved interrupt 39 */
INT_I2C0 = 40, /**< I2C0 interrupt */
INT_I2C1 = 41, /**< I2C1 interrupt */
INT_SPI0 = 42, /**< SPI0 Interrupt */
INT_SPI1 = 43, /**< SPI1 Interrupt */
INT_SPI2 = 44, /**< SPI2 Interrupt */
INT_CAN0_ORed_Message_buffer = 45, /**< CAN0 OR'd Message Buffers Interrupt */
INT_CAN0_Bus_Off = 46, /**< CAN0 Bus Off Interrupt */
INT_CAN0_Error = 47, /**< CAN0 Error Interrupt */
INT_CAN0_Tx_Warning = 48, /**< CAN0 Tx Warning Interrupt */
INT_CAN0_Rx_Warning = 49, /**< CAN0 Rx Warning Interrupt */
INT_CAN0_Wake_Up = 50, /**< CAN0 Wake Up Interrupt */
INT_Reserved51 = 51, /**< Reserved interrupt 51 */
INT_Reserved52 = 52, /**< Reserved interrupt 52 */
INT_CAN1_ORed_Message_buffer = 53, /**< CAN1 OR'd Message Buffers Interrupt */
INT_CAN1_Bus_Off = 54, /**< CAN1 Bus Off Interrupt */
INT_CAN1_Error = 55, /**< CAN1 Error Interrupt */
INT_CAN1_Tx_Warning = 56, /**< CAN1 Tx Warning Interrupt */
INT_CAN1_Rx_Warning = 57, /**< CAN1 Rx Warning Interrupt */
INT_CAN1_Wake_Up = 58, /**< CAN1 Wake Up Interrupt */
INT_Reserved59 = 59, /**< Reserved interrupt 59 */
INT_Reserved60 = 60, /**< Reserved interrupt 60 */
INT_UART0_RX_TX = 61, /**< UART0 Receive/Transmit interrupt */
INT_UART0_ERR = 62, /**< UART0 Error interrupt */
INT_UART1_RX_TX = 63, /**< UART1 Receive/Transmit interrupt */
INT_UART1_ERR = 64, /**< UART1 Error interrupt */
INT_UART2_RX_TX = 65, /**< UART2 Receive/Transmit interrupt */
INT_UART2_ERR = 66, /**< UART2 Error interrupt */
INT_UART3_RX_TX = 67, /**< UART3 Receive/Transmit interrupt */
INT_UART3_ERR = 68, /**< UART3 Error interrupt */
INT_UART4_RX_TX = 69, /**< UART4 Receive/Transmit interrupt */
INT_UART4_ERR = 70, /**< UART4 Error interrupt */
INT_UART5_RX_TX = 71, /**< UART5 Receive/Transmit interrupt */
INT_UART5_ERR = 72, /**< UART5 Error interrupt */
INT_ADC0 = 73, /**< ADC0 interrupt */
INT_ADC1 = 74, /**< ADC1 interrupt */
INT_CMP0 = 75, /**< CMP0 interrupt */
INT_CMP1 = 76, /**< CMP1 interrupt */
INT_CMP2 = 77, /**< CMP2 interrupt */
INT_FTM0 = 78, /**< FTM0 fault, overflow and channels interrupt */
INT_FTM1 = 79, /**< FTM1 fault, overflow and channels interrupt */
INT_FTM2 = 80, /**< FTM2 fault, overflow and channels interrupt */
INT_CMT = 81, /**< CMT interrupt */
INT_RTC = 82, /**< RTC interrupt */
INT_Reserved83 = 83, /**< Reserved interrupt 83 */
INT_PIT0 = 84, /**< PIT timer channel 0 interrupt */
INT_PIT1 = 85, /**< PIT timer channel 1 interrupt */
INT_PIT2 = 86, /**< PIT timer channel 2 interrupt */
INT_PIT3 = 87, /**< PIT timer channel 3 interrupt */
INT_PDB0 = 88, /**< PDB0 Interrupt */
INT_Reserved89 = 89, /**< Reserved interrupt 89 */
INT_Reserved90 = 90, /**< Reserved interrupt 90 */
INT_Reserved91 = 91, /**< Reserved interrupt 91 */
INT_Reserved92 = 92, /**< Reserved interrupt 92 */
INT_Reserved93 = 93, /**< Reserved interrupt 93 */
INT_Reserved94 = 94, /**< Reserved interrupt 94 */
INT_I2S0 = 95, /**< I2S0 Interrupt */
INT_SDHC = 96, /**< SDHC Interrupt */
INT_DAC0 = 97, /**< DAC0 interrupt */
INT_DAC1 = 98, /**< DAC1 interrupt */
INT_TSI0 = 99, /**< TSI0 Interrupt */
INT_MCG = 100, /**< MCG Interrupt */
INT_LPTimer = 101, /**< LPTimer interrupt */
INT_LCD = 102, /**< Segment LCD Interrupt */
INT_PORTA = 103, /**< Port A interrupt */
INT_PORTB = 104, /**< Port B interrupt */
INT_PORTC = 105, /**< Port C interrupt */
INT_PORTD = 106, /**< Port D interrupt */
INT_PORTE = 107, /**< Port E interrupt */
INT_Reserved108 = 108, /**< Reserved interrupt 108 */
INT_Reserved109 = 109, /**< Reserved interrupt 109 */
INT_Reserved110 = 110, /**< Reserved interrupt 110 */
INT_Reserved111 = 111, /**< Reserved interrupt 111 */
INT_Reserved112 = 112, /**< Reserved interrupt 112 */
INT_Reserved113 = 113, /**< Reserved interrupt 113 */
INT_Reserved114 = 114, /**< Reserved interrupt 114 */
INT_Reserved115 = 115, /**< Reserved interrupt 115 */
INT_Reserved116 = 116, /**< Reserved interrupt 116 */
INT_Reserved117 = 117, /**< Reserved interrupt 117 */
INT_Reserved118 = 118, /**< Reserved interrupt 118 */
INT_Reserved119 = 119 /**< Reserved interrupt 119 */
} IRQInterruptIndex;
/**
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Peripheral type defines
---------------------------------------------------------------------------- */
/**
* @addtogroup Peripheral_defines Peripheral type defines
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