?? mk30dz10.h
字號:
#define ADC_PGA_PGAEN_SHIFT 23
/* CLMD Bit Fields */
#define ADC_CLMD_CLMD_MASK 0x3Fu
#define ADC_CLMD_CLMD_SHIFT 0
#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
/* CLMS Bit Fields */
#define ADC_CLMS_CLMS_MASK 0x3Fu
#define ADC_CLMS_CLMS_SHIFT 0
#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
/* CLM4 Bit Fields */
#define ADC_CLM4_CLM4_MASK 0x3FFu
#define ADC_CLM4_CLM4_SHIFT 0
#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
/* CLM3 Bit Fields */
#define ADC_CLM3_CLM3_MASK 0x1FFu
#define ADC_CLM3_CLM3_SHIFT 0
#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
/* CLM2 Bit Fields */
#define ADC_CLM2_CLM2_MASK 0xFFu
#define ADC_CLM2_CLM2_SHIFT 0
#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
/* CLM1 Bit Fields */
#define ADC_CLM1_CLM1_MASK 0x7Fu
#define ADC_CLM1_CLM1_SHIFT 0
#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
/* CLM0 Bit Fields */
#define ADC_CLM0_CLM0_MASK 0x3Fu
#define ADC_CLM0_CLM0_SHIFT 0
#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
/**
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base pointer */
#define ADC0_BASE_PTR ((ADC_MemMapPtr)0x4003B000u)
/** Peripheral ADC1 base pointer */
#define ADC1_BASE_PTR ((ADC_MemMapPtr)0x400BB000u)
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register instance definitions */
/* ADC0 */
#define ADC0_SC1A ADC_SC1_REG(ADC0_BASE_PTR,0)
#define ADC0_SC1B ADC_SC1_REG(ADC0_BASE_PTR,1)
#define ADC0_CFG1 ADC_CFG1_REG(ADC0_BASE_PTR)
#define ADC0_CFG2 ADC_CFG2_REG(ADC0_BASE_PTR)
#define ADC0_RA ADC_R_REG(ADC0_BASE_PTR,0)
#define ADC0_RB ADC_R_REG(ADC0_BASE_PTR,1)
#define ADC0_CV1 ADC_CV1_REG(ADC0_BASE_PTR)
#define ADC0_CV2 ADC_CV2_REG(ADC0_BASE_PTR)
#define ADC0_SC2 ADC_SC2_REG(ADC0_BASE_PTR)
#define ADC0_SC3 ADC_SC3_REG(ADC0_BASE_PTR)
#define ADC0_OFS ADC_OFS_REG(ADC0_BASE_PTR)
#define ADC0_PG ADC_PG_REG(ADC0_BASE_PTR)
#define ADC0_MG ADC_MG_REG(ADC0_BASE_PTR)
#define ADC0_CLPD ADC_CLPD_REG(ADC0_BASE_PTR)
#define ADC0_CLPS ADC_CLPS_REG(ADC0_BASE_PTR)
#define ADC0_CLP4 ADC_CLP4_REG(ADC0_BASE_PTR)
#define ADC0_CLP3 ADC_CLP3_REG(ADC0_BASE_PTR)
#define ADC0_CLP2 ADC_CLP2_REG(ADC0_BASE_PTR)
#define ADC0_CLP1 ADC_CLP1_REG(ADC0_BASE_PTR)
#define ADC0_CLP0 ADC_CLP0_REG(ADC0_BASE_PTR)
#define ADC0_PGA ADC_PGA_REG(ADC0_BASE_PTR)
#define ADC0_CLMD ADC_CLMD_REG(ADC0_BASE_PTR)
#define ADC0_CLMS ADC_CLMS_REG(ADC0_BASE_PTR)
#define ADC0_CLM4 ADC_CLM4_REG(ADC0_BASE_PTR)
#define ADC0_CLM3 ADC_CLM3_REG(ADC0_BASE_PTR)
#define ADC0_CLM2 ADC_CLM2_REG(ADC0_BASE_PTR)
#define ADC0_CLM1 ADC_CLM1_REG(ADC0_BASE_PTR)
#define ADC0_CLM0 ADC_CLM0_REG(ADC0_BASE_PTR)
/* ADC1 */
#define ADC1_SC1A ADC_SC1_REG(ADC1_BASE_PTR,0)
#define ADC1_SC1B ADC_SC1_REG(ADC1_BASE_PTR,1)
#define ADC1_CFG1 ADC_CFG1_REG(ADC1_BASE_PTR)
#define ADC1_CFG2 ADC_CFG2_REG(ADC1_BASE_PTR)
#define ADC1_RA ADC_R_REG(ADC1_BASE_PTR,0)
#define ADC1_RB ADC_R_REG(ADC1_BASE_PTR,1)
#define ADC1_CV1 ADC_CV1_REG(ADC1_BASE_PTR)
#define ADC1_CV2 ADC_CV2_REG(ADC1_BASE_PTR)
#define ADC1_SC2 ADC_SC2_REG(ADC1_BASE_PTR)
#define ADC1_SC3 ADC_SC3_REG(ADC1_BASE_PTR)
#define ADC1_OFS ADC_OFS_REG(ADC1_BASE_PTR)
#define ADC1_PG ADC_PG_REG(ADC1_BASE_PTR)
#define ADC1_MG ADC_MG_REG(ADC1_BASE_PTR)
#define ADC1_CLPD ADC_CLPD_REG(ADC1_BASE_PTR)
#define ADC1_CLPS ADC_CLPS_REG(ADC1_BASE_PTR)
#define ADC1_CLP4 ADC_CLP4_REG(ADC1_BASE_PTR)
#define ADC1_CLP3 ADC_CLP3_REG(ADC1_BASE_PTR)
#define ADC1_CLP2 ADC_CLP2_REG(ADC1_BASE_PTR)
#define ADC1_CLP1 ADC_CLP1_REG(ADC1_BASE_PTR)
#define ADC1_CLP0 ADC_CLP0_REG(ADC1_BASE_PTR)
#define ADC1_PGA ADC_PGA_REG(ADC1_BASE_PTR)
#define ADC1_CLMD ADC_CLMD_REG(ADC1_BASE_PTR)
#define ADC1_CLMS ADC_CLMS_REG(ADC1_BASE_PTR)
#define ADC1_CLM4 ADC_CLM4_REG(ADC1_BASE_PTR)
#define ADC1_CLM3 ADC_CLM3_REG(ADC1_BASE_PTR)
#define ADC1_CLM2 ADC_CLM2_REG(ADC1_BASE_PTR)
#define ADC1_CLM1 ADC_CLM1_REG(ADC1_BASE_PTR)
#define ADC1_CLM0 ADC_CLM0_REG(ADC1_BASE_PTR)
/* ADC - Register array accessors */
#define ADC0_SC1(index) ADC_SC1_REG(ADC0_BASE_PTR,index)
#define ADC1_SC1(index) ADC_SC1_REG(ADC1_BASE_PTR,index)
#define ADC0_R(index) ADC_R_REG(ADC0_BASE_PTR,index)
#define ADC1_R(index) ADC_R_REG(ADC1_BASE_PTR,index)
/**
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/**
* @}
*/ /* end of group ADC_Peripheral */
/* ----------------------------------------------------------------------------
-- AIPS
---------------------------------------------------------------------------- */
/**
* @addtogroup AIPS_Peripheral AIPS
* @{
*/
/** AIPS - Peripheral register structure */
typedef struct AIPS_MemMap {
uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
uint8_t RESERVED_0[28];
uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
uint8_t RESERVED_1[16];
uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
} volatile *AIPS_MemMapPtr;
/* ----------------------------------------------------------------------------
-- AIPS - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
* @{
*/
/* AIPS - Register accessors */
#define AIPS_MPRA_REG(base) ((base)->MPRA)
#define AIPS_PACRA_REG(base) ((base)->PACRA)
#define AIPS_PACRB_REG(base) ((base)->PACRB)
#define AIPS_PACRC_REG(base) ((base)->PACRC)
#define AIPS_PACRD_REG(base) ((base)->PACRD)
#define AIPS_PACRE_REG(base) ((base)->PACRE)
#define AIPS_PACRF_REG(base) ((base)->PACRF)
#define AIPS_PACRG_REG(base) ((base)->PACRG)
#define AIPS_PACRH_REG(base) ((base)->PACRH)
#define AIPS_PACRI_REG(base) ((base)->PACRI)
#define AIPS_PACRJ_REG(base) ((base)->PACRJ)
#define AIPS_PACRK_REG(base) ((base)->PACRK)
#define AIPS_PACRL_REG(base) ((base)->PACRL)
#define AIPS_PACRM_REG(base) ((base)->PACRM)
#define AIPS_PACRN_REG(base) ((base)->PACRN)
#define AIPS_PACRO_REG(base) ((base)->PACRO)
#define AIPS_PACRP_REG(base) ((base)->PACRP)
/**
* @}
*/ /* end of group AIPS_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- AIPS Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup AIPS_Register_Masks AIPS Register Masks
* @{
*/
/* MPRA Bit Fields */
#define AIPS_MPRA_MPL5_MASK 0x100u
#define AIPS_MPRA_MPL5_SHIFT 8
#define AIPS_MPRA_MTW5_MASK 0x200u
#define AIPS_MPRA_MTW5_SHIFT 9
#define AIPS_MPRA_MTR5_MASK 0x400u
#define AIPS_MPRA_MTR5_SHIFT 10
#define AIPS_MPRA_MPL4_MASK 0x1000u
#define AIPS_MPRA_MPL4_SHIFT 12
#define AIPS_MPRA_MTW4_MASK 0x2000u
#define AIPS_MPRA_MTW4_SHIFT 13
#define AIPS_MPRA_MTR4_MASK 0x4000u
#define AIPS_MPRA_MTR4_SHIFT 14
#define AIPS_MPRA_MPL3_MASK 0x10000u
#define AIPS_MPRA_MPL3_SHIFT 16
#define AIPS_MPRA_MTW3_MASK 0x20000u
#define AIPS_MPRA_MTW3_SHIFT 17
#define AIPS_MPRA_MTR3_MASK 0x40000u
#define AIPS_MPRA_MTR3_SHIFT 18
#define AIPS_MPRA_MPL2_MASK 0x100000u
#define AIPS_MPRA_MPL2_SHIFT 20
#define AIPS_MPRA_MTW2_MASK 0x200000u
#define AIPS_MPRA_MTW2_SHIFT 21
#define AIPS_MPRA_MTR2_MASK 0x400000u
#define AIPS_MPRA_MTR2_SHIFT 22
#define AIPS_MPRA_MPL1_MASK 0x1000000u
#define AIPS_MPRA_MPL1_SHIFT 24
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