inferred   3 Counter(s).	inferred   1 D-type flip-flop(s).	inferred   5 Comparator(s).	inferred   3 Tristate(s).Unit <smartcard> synthesized.Synthesizing Unit <lcd>.    Related source file is C:/work/app/smartcard/smartcard/lcd.vhd.    Found finite state machine <FSM_3> for signal <CurrentState>.    -----------------------------------------------------------------------    | States             | 6                                              |    | Transitions        | 15                                             |    | Inputs             | 6                                              |    | Outputs            | 4                                              |    | Reset type         | asynchronous                                   |    | Encoding           | automatic                                      |    | State register     | d  flip-flops                                  |    -----------------------------------------------------------------------    Found 17-bit comparator greatequal for signal <$n0013> created at line 103.    Found 4-bit up counter for signal <bitcounter>.    Found 8-bit register for signal <DB_reg>.    Summary:	inferred   1 Finite State Machine(s).	inferred   1 Counter(s).	inferred   1 Comparator(s).Unit <lcd> synthesized.Synthesizing Unit <top>.    Related source file is C:/work/app/smartcard/smartcard/top.vhd.WARNING:Xst:646 - Signal <sc_vpp> is assigned but never used.WARNING:Xst:1780 - Signal <sram_w> is never used or assigned.WARNING:Xst:646 - Signal <sc_vcc> is assigned but never used.    Found finite state machine <FSM_4> for signal <CurrentState>.    -----------------------------------------------------------------------    | States             | 43                                             |    | Transitions        | 84                                             |    | Inputs             | 8                                              |    | Outputs            | 10                                             |    | Reset type         | asynchronous                                   |    | Encoding           | automatic                                      |    | State register     | d  flip-flops                                  |    -----------------------------------------------------------------------    Found 8-bit tristate buffer for signal <sram_db>.    Found 9-bit comparator greater for signal <$n0086> created at line 641.    Found 9-bit comparator less for signal <$n0087> created at line 641.    Found 9-bit comparator greater for signal <$n0088> created at line 641.    Found 9-bit comparator less for signal <$n0089> created at line 641.    Found 5-bit up counter for signal <Addr>.    Found 24-bit up counter for signal <counter>.    Summary:	inferred   1 Finite State Machine(s).	inferred   2 Counter(s).	inferred   4 Comparator(s).	inferred   8 Tristate(s).Unit <top> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# FSMs                             : 5# Registers                        : 3  10-bit register                  : 1  8-bit register                   : 1  1-bit register                   : 1# Counters                         : 10  16-bit up counter                : 1  24-bit up counter                : 1  8-bit down counter               : 1  4-bit up counter                 : 4  9-bit up counter                 : 1  8-bit up counter                 : 1  5-bit up counter                 : 1# Multiplexers                     : 1  2-to-1 multiplexer               : 1# Tristates                        : 4  1-bit tristate buffer            : 3  8-bit tristate buffer            : 1# Comparators                      : 12  17-bit comparator greatequal     : 2  9-bit comparator greater         : 4  9-bit comparator less            : 4  5-bit comparator greatequal      : 1  9-bit comparator greatequal      : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *=========================================================================Selecting encoding for FSM_4 ...	Encoding for FSM_4 is Gray flip-flop = DSelecting encoding for FSM_3 ...	Encoding for FSM_3 is Sequential flip-flop = DSelecting encoding for FSM_2 ...	Encoding for FSM_2 is Sequential flip-flop = DSelecting encoding for FSM_1 ...	Encoding for FSM_1 is Gray flip-flop = DSelecting encoding for FSM_0 ...	Encoding for FSM_0 is Sequential flip-flop = D=========================================================================*                         Low Level Synthesis                           *=========================================================================WARNING:Xst:1348 - Unit smartcard is merged (output interface has tristates)WARNING:Xst:637 - Naming conflict between signal Clk of unit Addr and signal Addr_Clk of unit top : renaming Addr_Clk to Addr_Clk1.WARNING:Xst:637 - Naming conflict between signal Clk of unit Bytecounter and signal Bytecounter_Clk of unit smartcard : renaming Bytecounter_Clk to Bytecounter_Clk1.WARNING:Xst:637 - Naming conflict between signal Clk of unit Bitcounter and signal Bitcounter_Clk of unit smartcard : renaming Bitcounter_Clk to Bitcounter_Clk1.Optimizing unit <top> ...  implementation constraint: NOREDUCE	 : smartcard_module_card_io  implementation constraint: KEEP	 : lcd_wOptimizing unit <conver2ascii> ...Optimizing unit <power_up> ...Optimizing unit <lcd> ...=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : top.ngrTop Level Output File Name         : topOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : YESTarget Technology                  : xbrMacro Preserve                     : YESXOR Preserve                       : YESClock Enable                       : YESwysiwyg                            : NODesign Statistics# IOs                              : 42Macro Statistics :# Registers                        : 289#      1-bit register              : 289# Tristates                        : 4#      1-bit tristate buffer       : 3#      8-bit tristate buffer       : 1# Comparators                      : 12#      17-bit comparator greatequal: 2#      5-bit comparator greatequal : 1#      9-bit comparator greatequal : 1#      9-bit comparator greater    : 4#      9-bit comparator less       : 4# Xors                             : 230#      1-bit xor2                  : 230Cell Usage :# BELS                             : 2301#      AND2                        : 744#      AND3                        : 147#      AND4                        : 56#      AND5                        : 13#      AND6                        : 3#      AND8                        : 11#      GND                         : 2#      INV                         : 983#      OR2                         : 228#      OR3                         : 24#      OR4                         : 2#      VCC                         : 1#      XOR2                        : 87# FlipFlops/Latches                : 123#      FD                          : 8#      FDC                         : 61#      FDCE                        : 54# IO Buffers                       : 42#      IBUF                        : 3#      IOBUFE                      : 9#      OBUF                        : 30=========================================================================CPU : 8.89 / 9.39 s | Elapsed : 9.00 / 9.00 s --> Total memory usage is 65124 kilobytes