JDF G
// Created by Project Navigator ver 1.0
PROJECT smartcard
DESIGN smartcard
DEVFAM xbr
DEVFAMTIME 0
DEVICE xc2c256
DEVICETIME 0
DEVPKG TQ144
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE top.vhd
SOURCE conver2ascii.vhd
SOURCE smartcard.vhd
SOURCE power_up.vhd
SOURCE lcd.vhd
DEPASSOC top top.ucf
[Normal]
xcpldFitDesVolt=xstvhd, xbr, VHDL.t_go, 1068167307, LVCMOS33
[STATUS-ALL]
top.ngcFile=WARNINGS,1068167572
[STRATEGY-LIST]
Normal=True