----------------------------------------------------------------------------------
-- Company: 		Hiline
-- Engineer: 		Liu Xiting
-- Email:			Liu_xitin@163.com;liuxiting@foxmail.com
-- 
-- Create Date:     21:13:54 01/03/2008 
-- Design Name: 	N.x frequency deviation
-- Module Name:		mux_21 
-- Project Name:	NdotXfd
-- Target Devices:	EP1C6Q240C8 or other FPGA/CPLD Device
-- Tool versions: 	Quartus II 7.2
-- Description:		21mux
--					y=a (if s=1);
--					y=b (if s=0);
--
-- Dependencies: 	none
--
-- Revision:		V1.0
--
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity mux_21 is
	port(
		a	: in  std_logic;
		b	: in  std_logic;
		s	: in  std_logic;
		y	: out std_logic
	);
end entity;

architecture bhv of mux_21 is
	
	begin
	
	with s select
	y <= a when '1' ,
		 b when others;
		
end bhv;