//*****************************************************************************
//             The following will handle the S5335 FIFO Operation 
//*****************************************************************************

assign n_wrfifo = wrfull  | fifo_dis;
//assign n_rdfifo = rdempty | fifo_dis;
assign n_rdfifo = rdempty | nrdfifo;

// *********************** Sequential Logic begins here ***********************

//*****************************************************************************
//             The following will handle the S5335 Pass-Thru Operation 
//*****************************************************************************
reg [16:0] mad;
always @( posedge bpclk or negedge n_sysrst )  begin
  if      ( !n_sysrst )  mad  <= 0;
  else if ( !n_ptadr  )  mad  <= {ptnum[1:0],dq[16:2]}; // Pass-Thru Read/Write
//  else if ( !n_ptrdy | !fifo_req )  mad  <= mad + 1;    // Address incremented
  else if ( !n_ptrdy | !n_rdfifo | !n_wrfifo )  mad  <= mad + 1;    // Address incremented
end

////////////////////////////////////////////////////////////////////////////////
// S0: if Pass-Thru Attention asserted, goto S1 else stay in S0
// S1: negate n_ptadr and check for read (S2) or write (S4)
// S2: pass-thru read turn around cycle to avoid DQ bus contention then goto S3
// S3: negate signals for read and goto end (S5)
// S4: pass-thru write cycle and goto S5
// S5: terminate pass-thru cycle and goto S0

reg n_ptrdy;
reg n_ptadr;
reg [2:0] pt_ctrl;
always @( posedge bpclk or negedge n_sysrst )  begin
  if ( !n_sysrst ) begin
    pt_rd     <= 1;
    pt_wr     <= 1;
    n_ptrdy   <= 1;
    n_ptadr   <= 1;
    pt_ctrl   <= 0;
    pt_select <= 1;
  end
  else begin
    case ( pt_ctrl )
      4'd0:  begin
               if ( !n_ptatn ) begin
                 n_ptadr   <= 0;
                 pt_ctrl   <= 1;
                 pt_select <= 0;
               end
               else  pt_ctrl <= 0;
             end
      4'd1:  begin
               n_ptadr <= 1;
               if ( ptwr ) begin 
                 pt_ctrl <= 4;      // Check for Write Cycle
                 pt_rd   <= 0;  end
               else  pt_ctrl <= 2;  // Goto Read Cycle
             end
      4'd2:  begin
               pt_wr   <= 0;
               n_ptrdy <= 0;
               pt_ctrl <= 3;
             end
      4'd3:  begin
               pt_wr   <= 1;
               n_ptrdy <= 1;
               pt_ctrl <= 5;
             end
      4'd4:  begin                  // Write Cycle
               pt_rd   <= 1;
               n_ptrdy <= 0;
               pt_ctrl <= 5;
             end
      4'd5:  begin
               n_ptrdy   <= 1;
               pt_ctrl   <= 0;
               pt_select <= 1;
             end
      default: begin pt_ctrl <= 0; n_ptrdy <= 1;  end
    endcase
  end  // end else
end // end always@

////////////////////////////////////////////////////////////////////////////////
// S0: if  uC accessing Add-On goto S1 else stay at S0
// S1: Add-On access, assert signals and check for read or write
// S2: negate signals & wait for R/W to negate then goto S0

reg [1:0] ao_ctrl;
always @( posedge bpclk or negedge n_sysrst )  begin
  if ( !n_sysrst ) begin
    ao_rd     <= 1;
    ao_wr     <= 1;
    ao_be     <= 1;
    ao_ctrl   <= 0;
    ao_select <= 1;
  end
  else begin
    case ( ao_ctrl )
      2'd0:  begin
               if ( ( !uc_wr | !uc_rd ) & !uc_addr[7] ) ao_ctrl <= 1;
               else                                     ao_ctrl <= 0;
             end
      2'd1:  begin
               ao_select <= 0;
               ao_be     <= 0;
               ao_ctrl   <= 2;
               if ( uc_wr ) ao_rd <= 0;
               else         ao_wr <= 0;
             end
      2'd2:  begin
                 ao_rd     <= 1;
                 ao_wr     <= 1;
                 ao_be     <= 1;
                 ao_select <= 1;
                 ao_ctrl   <= 3;
               if ( uc_wr & uc_rd ) ao_ctrl <= 0;
               else                 ao_ctrl <= 2;
             end
      default: begin ao_ctrl <= 0;  end
    endcase
  end  // end else
end // end always@

// ********** BE[3:0] needs 3ns hold time ***************
always @( negedge bpclk or negedge n_sysrst ) begin
  if ( !n_sysrst ) aobe <= 1;
  else             aobe <= ao_be;
end

// ********** latch data from Add-On interface ***************
reg [15:0] ao_rd_data;
always @( posedge bpclk or negedge n_sysrst ) begin
  if      ( !n_sysrst ) ao_rd_data <= 0;
  else if ( !ao_rd )    ao_rd_data <= dq[15:0];
end

///////////////////////////////////////////////////////////////////////////////
// Add-On Outgoing Mailbox, Byte 3 Access
// latch EA[7:0] into AOMB[4] when EA8 (LOAD) is sampled low to high by BPCLK

wire [7:0] mb3_wr_data;

assign ea8 = wr_mb3 & !uc_wr;
assign ea  = ( !ea8 ) ? mb3_wr_data : 8'hzz;

// ****************************************************************************
// Atmel microcontroller interface section
// ****************************************************************************

// Drive Data out of CPLD when read is asserted, read is active low
wire [7:0] uc_ad = ( !uc_rd ) ? uc_rd_data : 8'hzz;

///////////////////////////////////////////////////////////////////////////////
//
reg [2:0] ale_cntr;
always @( posedge bpclk or negedge n_sysrst)  begin
  if      ( !n_sysrst ) ale_cntr <= 0;
  else if ( uc_ale )    ale_cntr <= ale_cntr + 1;
  else                  ale_cntr <= 0;
end

///////////////////////////////////////////////////////////////////////////////
// valid addr on multiplexed addr/data bus when ALE goes high
// uC has a multiplexed addr/data bus, need to capture the addr on 1st cycle
always @( posedge bpclk or negedge n_sysrst)  begin
  if      ( !n_sysrst )                  uc_addr <= 8'h80;
  else if ( !ale_cntr[1] & ale_cntr[2] ) uc_addr <= uc_ad;
end

///////////////////////////////////////////////////////////////////////////////
//reg rd_dly1, rd_dly2, uc_read, rd_edge;
reg rd_dly1, rd_dly2, uc_read;
always @( posedge bpclk or negedge n_sysrst ) begin
  if ( !n_sysrst ) begin
    rd_dly1 <= 0; 
    rd_dly2 <= 0; 
    uc_read <= 0; 
    rd_edge <= 0;
    nrdfifo <= 0;
  end
  else begin
    nrdfifo <= rdempty | fifo_dis;
    rd_dly1 <= uc_rd; 
    rd_dly2 <= rd_dly1; 
    uc_read <= rd_dly2;
    if ( uc_read && !rd_dly2 ) rd_edge <= 1;
    else                       rd_edge <= 0;
  end
end

reg wr_dly1, uc_write;
always @( posedge bpclk or negedge n_sysrst ) begin
  if ( !n_sysrst ) begin
    wr_dly1  <= 0; 
    uc_write <= 0; 
    wr_edge  <= 0;
  end
  else begin
    wr_dly1  <= uc_wr; 
    uc_write <= wr_dly1;
    if ( uc_write && !wr_dly1 ) wr_edge <= 1;
    else                        wr_edge <= 0;
  end
end


// ****************************************************************************
// ***************************  BEGIN INSTANTIATIONS **************************
// ****************************************************************************

uc_if   uc_if (
  .uc_clk            ( bpclk ),
  .resetn            ( n_sysrst ),
  .uc_rd             ( rd_edge ),
  .uc_wr             ( wr_edge ),
  .uc_addr           ( uc_addr ),
  .uc_wr_data        ( uc_ad ),
  .uc_rd_data        ( uc_rd_data ),
  .wrfull            ( wrfull ),
  .rdempty           ( rdempty ),
  .fwe               ( fwe ),
  .frf               ( frf ),
  .n_frc             ( n_frc ),
  .n_fwc             ( n_fwc ),
  .wr_mb3            ( wr_mb3 ),
  .amwen             ( amwen ),
  .amren             ( amren ),
  .mode              ( mode ),
  .fifo_dis          ( fifo_dis ),
  .mb3_wr_data       ( mb3_wr_data ),
  .ao_wr_data        ( ao_wr_data ),
  .ao_rd_data        ( ao_rd_data )
);

///////////////////////////////////////////////////////////////////////////////

endmodule